PHT11N06LT Datasheet, PDF (5/9 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHT11N06LT
20
ID/A
15
10
Tj/C =
150
25
5
0
0
1
2 _VGS/V 3
4
Fig.7. Typical transfer characteristics.
I_D = f(V_GS) ; conditions: V_DS = 25 V; parameter T_j
Transconductance, gfs (S)
25
20
15
10
5 _{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20}
Drain current, ID (A)
Fig.8. Typical transconductance, T_j = 25 ˚C.
g_fs = f(I_D); conditions: V_DS = 25 V
2.5 ^a
BUK98XX-55
Rds(on) normalised to 25degC
2
1.5
1
0.5
-100
-50
0
50
100
150
200
Tmb / degC
Fig.9. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j); I_D = 5 A; V_GS = 5 V
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
BUK98xx-55
0.5
0
-100
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2%
typ
98%
1E-04
1E-05
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
2.5
2.0
1.5
1.0
Ciss
0.5
0
0.01
0.1
1 _VDS/V 10
Coss
Crss
100
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
January 1998
5
Rev 1.100