PHP55N03LT Datasheet, PDF (5/11 Pages) NXP Semiconductors – N-channel TrenchMOS transistor Logic level FET

Philips Semiconductors
N-channel TrenchMOS™ transistor
Logic level FET
Product specification
PHP55N03LT, PHB55N03LT
PHD55N03LT
Drain current, ID (A)
1.0E-01
VDS = 5 V
1.0E-02
1.0E-03
1.0E-04
minimum
typical
maximum
1.0E-05
1.0E-06
0
0.5
1
1.5
2
2.5
3
Gate-source voltage, VGS (V)
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
Capacitances, Ciss, Coss, Crss (pF)
10000
Ciss
1000
Coss
Crss
100
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
Gate-source voltage, VGS (V)
15
14 ^{ID = 55A}
13 _{Tj = 25 C}
12
11 ^{VDD = 15 V}
10
9
8
7
6
5
4
3
2
1
0
0
5
10 15 20 25 30 35 40 45 50
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); parameter V_DS
Source-Drain Diode Current, IF (A)
50
VGS = 0 V
45
40
35
30
175 C
25
Tj = 25 C
20
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
Fig.14. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
October 1999
5
Rev 1.200