PHP37N06LT Datasheet, PDF (5/10 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP37N06LT, PHB37N06LT, PHD37N06LT
2.5 ^a
BUK959-60 _{Rds(on) normlised to 25degC}
2
1.5
1
0.5
-100
-50
0
50
100
150
200
Tmb / degC
Fig.9. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j); I_D = 17 A; V_GS = 5 V
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
BUK959-60
0.5
0
-100
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2%
typ
98%
1E-04
1E-05
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
2.5
2.0
1.5
1.0
Ciss
0.5
0
0.01
0.1
1 _VDS/V 10
Coss
Crss
100
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
6
VGS/V
5
4
3
VDS = 14V
VDS = 44V
2
1
0
0
5
10 _QG/nC 15
20
25
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); conditions: I_D = 30 A; parameter V_DS
100
IF/A
80
60
Tj/C = 175
25
40
20
0
0
0.5
VSDS/V
1
1.5
Fig.14. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
September 1998
5
Rev 1.400