PCA9516 Datasheet, PDF (5/10 Pages) NXP Semiconductors – 5-channel I2C hub

Philips Semiconductors
5-channel I²C hub
9th CLOCK PULSE
Product data
PCA9516
2 V/DIV
V_OL OF MASTER
V_OL OF PCA9516
Figure 5. Bus 0 waveform
SW00965
On the Bus 1 side of the PCA9516, the clock and data lines would
have a positive offset from ground equal to the V_OL of the PCA9516.
After the 8th clock pulse, the data line will be pulled to the V_OL of the
slave device that is very close to ground in our example.
It is important to note that any arbitration or clock stretching events
on Bus 1 require that the V_OL of the devices on Bus 1 be 70 mV
below the V_OL of the PCA9516 (see V_OL – V_ilc in the DC
Characteristics section) to be recognized by the PCA9516 and then
transmitted to Bus 0.
9th CLOCK PULSE
2 V/DIV
V_OL OF SLAVE
Figure 6. Bus 1 waveform
V_OL OF PCA9516
SW00966
2002 May 13
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