OM5202 Datasheet, PDF (5/11 Pages) NXP Semiconductors – ROMless 8-bit microcontroller

Philips Semiconductors
ROMless 8-bit microcontroller
Product specification
OM5202
ROM CODE EXTERNAL (OM5202)
The MOVC instructions are the only instructions that have access to
program code in the external program memory. The EA input is
latched during RESET.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 2.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Reset
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V_DD and RST must come up at the same time for a proper start-up.
Idle Mode
In the idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
Power-Down Mode
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 2 shows the state of the I/O ports during low current
operating modes.
Table 2. External Pin Status During Idle and Power-Down Mode
MODE
PROGRAM
MEMORY
ALE
PSEN
PORT 0
Idle
External
1
1
Float
Power-down
External
0
0
Float
PORT 1
Data
Data
PORT 2
Address
Data
Serial Control Register (S1CON) – See Table 3
S1CON (D8H) CR2 ENS1 STA STO SI AA CR1 CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
PORT 3
Data
Data
Table 3.
CR2
0
0
0
0
1
1
1
1
Serial Clock Rates
CR1
0
0
1
1
0
0
1
1
CR0
0
1
0
1
0
1
0
1
BIT FREQUENCY (kHz) AT f_OSC
6MHz
12MHz
16MHz
23
27
31.25
37
6.25
50
100
0.24 < 62.5
0 to 255
47
54
62.5
75
12.5
100
200
0.49 < 62.5
0 to 254
62.5
71
83.3
100
17
133
267
0.65 < 55.6
0 to 253
f_OSC DIVIDED BY
256
224
192
160
960
120
60
96 × (256 – (reload value Timer 1))
reload value range Timer 1 (in mode 2)
December 1994
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