OM4068 Datasheet, PDF (5/28 Pages) NXP Semiconductors – LCD driver for low multiplex rates

Philips Semiconductors
LCD driver for low multiplex rates
Product specification
OM4068
SYMBOL
PIN
QFP44
DIP40
DESCRIPTION
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
42
13
LCD segment driver output 27
43
14
LCD segment driver output 28
44
15
LCD segment driver output 29
1
16
LCD segment driver output 30
2
17
LCD segment driver output 31
3
18
LCD segment driver output 32
Notes
1. SEG1 to SEG32 (LCD segment driver outputs) output the multi-level signals for the LCD segments.
2. BP0, BP1 and BP2 (LCD backplane driver outputs) output the multi-level signals for the LCD backplanes.
3. V_LCD (LCD power supply): power supply for the LCD.
4. SDIN (serial data line): input for the bus data line.
5. SCL (serial clock line): input for the bus clock line.
6. SDOUT (serial data output): output of the shift register to allow serial cascading of the OM4068 with other devices.
7. SCE (serial clock enable): input for enable/disable acquisition on the data input line. If disabled, data on the serial
bus are not accepted by the device.
8. M0 and M1 (display mode select inputs): inputs to select the LCD drive configurations; static, duplex or triplex.
1998 Jun 18
5