BUK102-50DL Datasheet, PDF (5/10 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK102-50DL
ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER
L_d
Internal drain inductance
L_d
Internal drain inductance
L_s
Internal source inductance
CONDITIONS
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
MIN. TYP. MAX. UNIT
-
3.5
-
nH
-
4.5
-
nH
-
7.5
-
nH
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.2. Normalised limiting power dissipation.
P_D% = 100⋅P_D/P_D(25 ˚C) = f(T_mb)
ID%
120
Normalised Current Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.3. Normalised continuous drain current.
I_D% = 100⋅I_D/I_D(25 ˚C) = f(T_mb); conditions: V_IS = 5 V
ID & IDM / A
1000
BUK102-50DL
Overload protection characteristics not shown
100
RDS(ON) ^{= VDS/ID}
tp =
100 us
10
DC
1 ms
10 ms
100 ms
1
1
10
100
VDS / V
Fig.4. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Zth / (K/W)
10
BUK102-50DL
1 ^D=
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0
P_D
tp
D
=
tp
T
0.001
1E-07
1E-05
1E-03
t/s
T
t
1E-01
Fig.5. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
1E+01
April 1993
5
Rev 1.100