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| 74ABT821 Datasheet, PDF (5/6 Pages) NXP Semiconductors – 10-bit D-type flip-flop; positive-edge trigger 3-State | |||
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Philips Semiconductors
10-bit D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74ABT821
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500â¦
SYMBOL
PARAMETER
WAVEFORM
ts(H)
ts(L)
Setup time, High or Low
Dn to CP
2
th(H)
th(L)
Hold time, High or Low
Dn to CP
2
tw(H)
tw(L)
CP pulse width
High or Low
1
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
1/fMAX
CP
VM
VM
tW(H)
tPHL
tW(L)
tPLH
Qn
VM
VM
SA00159
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
OE
VM
VM
tPZH
tPHZ
Qn
VM
VOHâ0.3V
0V
SA00066
Waveform 3. 3âState Output Enable Time to High Level and
Output Disable Time from High Level
LIMITS
Tamb = +25oC
VCC = +5.0V
Min
Typ
Tamb = -40 to +85oC
VCC = +5.0V ±0.5V
Min
2.1
0.5
2.1
2.1
0.3
2.1
1.3
0.0
1.3
1.3
â0.3
1.3
2.9
1.8
2.9
3.8
2.8
3.8
UNIT
ns
ns
ns
ÃÃÃ ÃÃÃÃÃÃÃÃÃ Dn
VM
ÃÃÃÃÃÃ ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ ts(H)
VM
th(H)
VM
ts(L)
VM
th(L)
CP
VM
VM
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
Waveform 2. Data Setup and Hold Times
SA00107
OE
VM
VM
tPZL
tPLZ
Qn
VM
VOL+0.3V
0V
SA00067
Waveform 4. 3âState Output Enable Time to Low Level and
Output Disable Time from Low Level
1995 Sep 06
5
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