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74ABT16374B Datasheet, PDF (5/10 Pages) NXP Semiconductors – 16-bit D-type flip-flop; positive-edge trigger 3-State | |||
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Philips Semiconductors
16-bit D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74ABT16374B
74ABTH16374B
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
Tamb = â40°C
to +85°C
UNIT
MIN TYP MAX MIN MAX
VIK
VOH
VOL
VRST
II
Input clamp voltage
High-level output voltage
Low-level output voltage
Power-up output voltage3
Input leakage current
74ABT16374B
VCC = 4.5V; IIK = â18mA
VCC = 4.5V; IOH = â3mA; VI = VIL or VIH
VCC = 5.0V; IOH = â3mA; VI = VIL or VIH
VCC = 4.5V; IOH = â32mA; VI = VIL or VIH
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
VCC = 5.5V; IO = 1mA; VI = GND or VCC
VCC = 5.5V; VI = VCC or GND
â0.9 â1.2
â1.2 V
2.5 2.9
2.5
3.0 3.4
3.0
V
2.0 2.4
2.0
0.42 0.55
0.55 V
0.13 0.55
0.55 V
0.01 ±1
±1
µA
II
Input leakage current
74ABTH16374B
VCC = 5.5V; VI = VCC or
GND
VCC = 5.5V; VI = VCC
VCC = 5.5V; VI = 0
Control pins
Data pins5
±0.01 ±1
0.01
1
â1
â3
±1
1
µA
â5
IHOLD
Bus Hold current inputs6
74ABTH16374B
VCC = 4.5V; VI = 0.8V
VCC = 4.5V; VI = 2.0V
VCC = 5.5V; VI = 0 to 5.5V
50
â75
±800
50
â75
µA
IOFF
Power-off leakage current VCC = 0.0V; VO or VI ⤠4.5V
±5.0 ±100
±100 µA
IPU/PD
Power-up/down 3-State
output current4
VCC = 2.1V; VO = 0.5V;
VI = GND or VCC; V OE = GND
±5.0 ±50
±50 µA
IOZH
3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
0.5
10
10
µA
IOZL
3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
â0.5 â10
â10 µA
ICEX
IO
Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC
Output current1
VCC = 5.5V; VO = 2.5V
5.0
50
50
µA
â50 â70 â180 â50 â180 mA
ICCH
VCC = 5.5V; Outputs High, VI = GND or VCC
0.5
2
2
mA
ICCL
Quiescent supply current
VCC = 5.5V; Outputs Low, VI = GND or VCC
8
19
19
mA
ICCZ
VCC = 5.5V; Outputs 3-State;
VI = GND or VCC
0.5
2
2
mA
âICC
Additional supply current
per input pin2
74ABT16374B
VCC = 5.5V; one input at 3.4V, other inputs at
VCC or GND
5
100
100 µA
âICC
Additional supply current
per input pin2
74ABTH16374B
VCC = 5.5V; one input at 3.4V, other inputs at
VCC or GND
0.5 1.5
1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a
transition time of up to 100µsec is permitted.
5. Unused pins at VCC or GND.
6. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
5
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