SAA7102 Datasheet, PDF (49/76 Pages) NXP Semiconductors – Digital video encoder

Philips Semiconductors
Digital video encoder
Product specification
SAA7102; SAA7103
Table 64 Subaddress 6DH
DATA BYTE
DESCRIPTION
VTRIG
sets the vertical trigger phase related to chip-internal vertical input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH); the default value is 0
Table 65 Subaddress 6EH
DATA BYTE
BLCKON
PHRES
LDEL
FLC
LOGIC
LEVEL
DESCRIPTION
0 encoder in normal operation mode; default after reset
1 output signal is forced to blanking level
− selects the phase reset mode of the colour subcarrier generator; see Table 66
− selects the delay on luminance path with reference to chrominance path; see Table 67
− field length control; see Table 68
Table 66 Logic levels and function of PHRES
DATA BYTE
PHRES1
0
0
1
1
PHRES0
0
1
0
1
no subcarrier reset
subcarrier reset every two lines
subcarrier reset every eight fields
subcarrier reset every four fields
DESCRIPTION
Table 67 Logic levels and function of LDEL
DATA BYTE
LDEL1
0
0
1
1
LDEL0
0
1
0
1
DESCRIPTION
no luminance delay; default after reset
1 LLC luminance delay
2 LLC luminance delay
3 LLC luminance delay
Table 68 Logic levels and function of FLC
DATA BYTE
FLC1
0
0
1
1
FLC0
0
1
0
1
DESCRIPTION
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
2001 Sep 25
49