P8XCE598 Datasheet, PDF(48/108 Page) NXP Semiconductors – 8-bit microcontroller with on-chip CAN

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P8XCE598 Datasheet, PDF (48/108 Pages) NXP Semiconductors – 8-bit microcontroller with on-chip CAN

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Philips Semiconductors

8-bit microcontroller with on-chip CAN

Product speciï¬cation

P8xCE598

Table 57 Description of the other DSCR2 bits

BIT

SYMBOL

FUNCTION

RTR

Remote Transmission Request. If the RTR bit is:

HIGH (remote), then the Remote Frame will be transmitted by the CAN-controller.

LOW (data), then the Data Frame will be transmitted by the CAN-controller.

DLC.3

DLC.2

DLC.1

DLC.0

Data Length Code (DLC). The number of bytes (Data Byte Count) in the Data Field of a

message is coded by the Data Length Code. At the start of a Remote Frame transmission

the Data Length Code is not considered due to the RTR bit being HIGH (remote). This

forces the number of transmitted/received data bytes to be a logic 0. Nevertheless, the

Data Length Code must be speciï¬ed correctly to avoid bus errors, if two CAN-controllers

start a Remote Frame transmission simultaneously. The range of the Data Byte Count is

0 to 8 bytes and coded as follows:

Data Byte Count = 8DLC.3 + 4DLC.2 + 2DLC.1 + DLC.0

For reasons of compatibility no Data Byte Counts other than 0,1,2,....,8 should be used.

13.5.13.2 Data Field

The number of transferred data bytes is determined by the

Data Length Code. The first bit transmitted is the most

significant bit of data byte 1 at address 12.

13.5.14 RECEIVE BUFFER LAYOUT

The layout of the Receive Buffer and the individual bytes

correspond to the definitions given for the Transmit Buffer

layout, except that the addresses start at 20 instead of 10

(see Fig.15).

13.5.15 HANDLING OF THE CPU-CAN INTERFACE

Via the four special registers CANADR, CANDAT,

CANCON and CANSTA the CPU has access to the

CAN-controller and also to the DMA-logic. Note that

CANCON and CANSTA have different meanings for a

Read and Write access.

Table 58 The SFRs between CPU and CAN

Reserved bits are read as HIGH. R = Read; W = Write; R/W = Read/Write.

BIT

ADDRESS ACCESS

CANADR

DBH

R/W

DMA

Reserved AutoInc CANA4 CANA3 CANA2 CANA1

CANDAT

DAH

R/W

CAND7 CAND6 CAND5 CAND4 CAND3 CAND2 CAND1

CANCON; Do not use a RMW instruction

D9H

Reserved Reserved Reserved WUI

RX0A

RX1A

WUM

SLP

COS

RRB

CANSTA; The bit addresses of CANSTA (7 to 0) are DFH to D8H; do not use a RMW instruction

DFH to D8H R

TCS

TBS

RAMA7 RAMA6 RAMA5 RAMA4 RAMA3 RAMA2 RAMA1

CANA0

CAND0

RBS

RAMA0

1996 Jun 27

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