P89V51RB2 Datasheet, PDF (45/77 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 16/32/64 kB Flash microcontroller with 1 kB RAM

Philips Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
To protect the system against software deadlock, the user software must refresh the
WDT within a user-defined time period. If the software fails to do this periodical
refresh, an internal hardware reset will be initiated if enabled (WDRE = 1). The
software can be designed such that the WDT times out if the program does not work
properly.
The WDT in the device uses the system clock (XTAL1) as its time base. So strictly
speaking, it is a Watchdog counter rather than a Watchdog timer. The WDT register
will increment every 344,064 crystal clocks. The upper 8-bits of the time base register
(WDTD) are used as the reload register of the WDT.
The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User
software can clear WDTS by writing ‘1' to it.
Figure 20 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD)
control Watchdog timer operation. During idle mode, WDT operation is temporarily
suspended, and resumes upon an interrupt exit from idle.
The time-out period of the WDT is calculated as follows:
Period = (255 − WDTD) × 344064 × 1/f_{CLK (XTAL1)}
where WDTD is the value loaded into the WDTD register and f_osc is the oscillator
frequency.
CLK (XTAL1)
external RST
344064
COUNTER ^clks
WDT
UPPER BYTE
WDT reset
internal reset
WDTC
WDTD
Fig 20. Block diagram of programmable Watchdog timer
002aaa531
Table 35: WDTC - Watchdog control register (address COH) bit allocation
Bit addressable; Reset value: 00H
Bit
7
6
5
4
3
2
1
Symbol
-
-
-
WDOUT WDRE WDTS WDT
0
SWDT
Table 36:
Bit
7 to 5
4
3
WDTC - Watchdog control register (address COH) bit description
Symbol Description
-
Reserved for future use. Should be set to ‘0’ by user programs.
WDOUT
Watchdog output enable. When this bit and WDRE are both set, a
Watchdog reset will drive the reset pin active for 32 clocks.
WDRE
Watchdog timer reset enable. When set enables a Watchdog timer
reset.
9397 750 14341
Product data
Rev. 03 — 02 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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