80C32 Datasheet, PDF (45/62 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontrollers

Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C52/80C54/80C58
SCON Address = 98H
Bit Addressable
SM0/FE SM1
SM2
REN
TB8
RB8
Tl
Bit:
7
6
5
4
3
2
1
(SMOD0 = 0/1)*
Reset Value = 0000 0000B
Rl
0
Symbol Function
FE
SM0
SM1
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0 SM1 Mode
Description Baud Rate**
0
0
0
1
1
0
1
1
0
shift register
f_OSC/12
1
8-bit UART
variable
2
9-bit UART
f_OSC/64 or f_OSC/32
3
9-bit UART
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0 is located at PCON6.
**f_OSC = oscillator frequency
SU00043
Figure 7. SCON: Serial Port Control Register
D0
D1
D2
D3
D4
D5
D6
D7
D8
START
BIT
DATA BYTE
ONLY IN STOP
MODE 2, 3 BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
SM0 / FE SM1
SM2
REN
TB8
RB8
TI
RI
SCON
(98H)
SMOD1 SMOD0
–
0 : SCON.7 = SM0
1 : SCON.7 = FE
POF
GF1
GF0
PD
Figure 8. UART Framing Error Detection
IDL
PCON
(87H)
SU00747
1996 Aug 16
15