SC16C852L Datasheet, PDF (42/60 Pages) NXP Semiconductors – 1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface

NXP Semiconductors
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Table 40. Dynamic characteristics - Motorola or 68 mode
T_amb = −40 °C to +85 °C; V_DD = 1.65 V to 1.95 V; unless otherwise specified.
Symbol
Parameter
Conditions
t_WH
t_WL
t_w(clk)
f_XTAL1
t_su(A)
t_h(A)
t_su(RWL-CSL)
t_su(RWH-CSL)
t_{d(stop-RXRDY)}
t_{d(start-TXRDY)}
t_w(CS)
t_d(CS)
t_d(CS-Q)
t_dis(CS-QZ)
pulse width HIGH
pulse width LOW
clock pulse width
frequency on pin XTAL1
address setup time
address hold time
set-up time from R/W LOW to CS LOW
set-up time from R/W HIGH to CS LOW
delay time from stop to RXRDY
delay time from start to TXRDY
CS pulse width
CS delay time
delay time from CS to data output
disable time from CS to high-impedance
data output
25 pF load
25 pF load
25 pF load
25 pF load
t_h(CS-RWH)
t_d(RW)
t_su(D-CSH)
t_h(CSH-D)
t_{d(modem-IRQL)}
t_d(CS-IRQH)R
t_d(stop-IRQL)
t_{d(CS-RXRDYH)R}
t_d(CS-TX)W
t_{d(start-IRQL)}
t_d(CS-IRQH)W
t_{d(CS-TXRDYH)W}
t_d(CS-Q)W
t_{w(RESET_N)}
N
hold time from CS to R/W HIGH
R/W delay time
set-up time from data input to CS HIGH
data input hold time after CS HIGH
delay time from modem to IRQ LOW
read delay time from CS to IRQ HIGH
delay time from stop to IRQ LOW
read delay time from CS to RXRDY HIGH
write delay time from CS to TX
delay time from start to IRQ LOW
write delay time from CS to IRQ HIGH
write delay time from CS to TXRDY HIGH
write delay time from CS to data output
pulse width on pin RESET
baud rate divisor
Min
Typ
6
-
6
-
12.5 -
[1][2] _-
-
5
-
10
-
10
-
10
-
[3] _-
-
[3] _-
-
20
-
10
-
-
-
-
-
5
-
10
-
5
-
5
-
-
-
-
-
[3] _-
-
-
-
[3] _{8TRCLK -}
[3] _-
-
-
-
-
-
-
-
10
-
1
-
[1] Applies to external clock, crystal oscillator max 24 MHz.
[2] Maximum frequency = -_t--_w---₍-¹-_c--_l--_k--₎
[3] RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Max
-
-
-
80
-
-
-
-
1T_RCLK
8T_RCLK
-
-
20
20
Unit
ns
ns
ns
MHz
ns
ns
ns
ns
s
s
ns
ns
ns
ns
-
ns
-
ns
-
ns
-
ns
50
ns
50
ns
1T_RCLK s
50
ns
24T_RCLK s
1T_RCLK s
50
ns
50
ns
50
ns
-
ns
(2¹⁶ − 1)
SC16C852L_2
Product data sheet
Rev. 02 — 25 January 2007
© NXP B.V. 2007. All rights reserved.
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