P89LPC938 Datasheet, PDF (42/68 Pages) NXP Semiconductors – 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable Flash with 10-bit A/D converter

Philips Semiconductors
P89LPC938
8-bit microcontroller with 10-bit A/D converter
7.25 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz Watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog feature is disabled, it can be used as an interval timer
and may generate an interrupt. Figure 20 shows the watchdog timer in Watchdog mode.
Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog
clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a
time-out period that ranges from a few µs to a few seconds. Please refer to the
P89LPC938 User’s Manual for more details.
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
watchdog
oscillator
÷32
PCLK
PRESCALER
WDL (C1H)
8-BIT DOWN
COUNTER
reset⁽¹⁾
SHADOW REGISTER
WDCON (A7H) PRE2 PRE1 PRE0
-
-
WDRUN WDTOF WDCLK
002aaa905
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 20. Watchdog timer in Watchdog mode (WDTE = ‘1’).
7.26 Additional features
7.26.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
7.26.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
9397 750 14051
Product data sheet
Rev. 01 — 25 February 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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