ISP1563 Datasheet, PDF (42/107 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

Philips Semiconductors
ISP1563
HS USB PCI Host Controller
Table 46: HcCommandStatus - Host Controller Command Status register bit allocation
Address: Value read from func0 or func1 of address 10h + 08h
Bit
31
30
29
28
27
26
Symbol
reserved ^[1]
Reset
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
18
Symbol
reserved ^[1]
Reset
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
10
Symbol
reserved ^[1]
Reset
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
Symbol
reserved ^[1]
OCR
BLF
Reset
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
[1] The reserved bits should always be written with the reset value.
25
24
0
0
R/W
R/W
17
16
SOC[1:0]
0
0
R/W
R/W
9
8
0
0
R/W
R/W
1
0
CLF
HCR
0
0
R/W
R/W
Table 47: HcCommandStatus - Host Controller Command Status register bit description
Address: Value read from func0 or func1 of address 10h + 08h
Bit
Symbol Description
31 to 18 reserved -
17 to 16
SOC[1:0]
Scheduling Overrun Count: The bit is incremented on each scheduling
overrun error. It is initialized to 00b and wraps around at 11b. It must be
incremented when a scheduling overrun is detected, even if SO (bit 0 in
HcInterruptStatus) is already set. This is used by the HCD to monitor any
persistent scheduling problems.
15 to 4 reserved -
3
OCR
Ownership Change Request: This bit is set by an OS HCD to request a
change of control of the Host Controller. When set, the Host Controller
must set OC (bit 30 in HcInterruptStatus). After the changeover, this bit is
cleared and remains so until the next request from the OS HCD.
9397 750 14224
Product data sheet
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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