SAA7705H Datasheet, PDF (40/60 Pages) NXP Semiconductors – Car radio Digital Signal Processor DSP

Philips Semiconductors
Car radio Digital Signal Processor (DSP)
Preliminary specification
SAA7705H
12.4 Register description
Table 7 DCSCTR register (address 0FFFH)
NAME
CLK-ISN-ONOFF
PLL-DIV
LOOPO-ONOFF
GAIN-HL
LOCKED-PRESET
F1-COEF
F0-COEF
SIZE
(BITS)
DESCRIPTION
1 ISN clock
1: off
0: on
4 PLL clock division factor (see Table 15)
1 Loopo
1: on
0: off
1 variable loop-gain stereo decoder
1: high
0: low
1 DCS clock
1: locked
0: preset
4 coarse division factor F1 (see Table 16)
4 coarse division factor F0 (see Table 16)
DEFAULT
1 (off)
BIT POSITION
15
1010 (154)
0 (off)
14 to 11
10
1 (high)
9
1 (locked)
8
0010 (F1 = 11)
0011
(F0 = 11.5)
7 to 4
3 to 0
Table 8 DCSDIV register (address 0FFEH)
NAME
DCS-COEF
SIZE
(BITS)
DESCRIPTION
16 Sigma-Delta modulator V (note 1)
DEFAULT
28EDH
BIT POSITION
15 to 0
Note
1. DCS-COEF can be calculated by the multiplication V × 2¹⁵ and then convert this decimal value to hexadecimal.
1999 Aug 16
40