UMA1016XT Datasheet, PDF (4/16 Pages) NXP Semiconductors – Frequency synthesizer for radio communication equipment

Philips Semiconductors
Frequency synthesizer for
radio communication equipment
Product specification
UMA1016xT
PINNING
SYMBOL
RO1
RO2
V_DD
REFCK
HPDN
DGND
RFI
i.c.
DATA
CK
EN
TX/RX
i.c.
AGND
V_CC
CP
PIN
DESCRIPTION
1 crystal oscillator input or TCXO
input
2 oscillator output to crystal circuit
3 5 V supply to digital section
4 reference crystal frequency
buffered output
5 Hardware Power-Down Not;
IC operates when pin is HIGH
6 digital ground
7 1 GHz RF signal input
8 internally connected
9 programming bus data input
10 programming bus clock input
11 programming bus enable input
(active LOW)
12 transmit (HIGH)/receive (LOW)
mode select input
13 internally connected
14 analog ground
15 5 V supply to charge pump
circuit
16 charge pump output
handbook, halfpage
RO1 1
16 CP
RO2 2
VDD ₃
15 VCC
14 AGND
REFCK 4
13 i.c.
UMA1016XT
HPDN ⁵
12 TX/RX
DGND 6
11 EN
RFI 7
10 CK
i.c. 8
9 DATA
MGA192 - 1
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
General
The UMA1016xT is a low power synthesizer for radio
communications in the range 500 to 1000 MHz. It includes
an oscillator circuit, reference divider, RF divider, 3-state
phase and frequency comparator, charge pump and main
control circuit for the transfer of serial data into two internal
registers.
V_DD supplies power to the digital circuits while V_CC powers
the charge pump. V_DD and V_CC are nominally 5 V but will
operate in the range 4.5 V to 5.5 V.
Reduced noise coupling is facilitated by separate digital
and analog ground pins which must always be externally
connected to the same DC potential to prevent the flow of
large currents across the die.
The synthesizer is placed in idle mode during power-down
but the oscillator and buffer remain operative and may be
used as a clock for system timing.
Main divider
The main divider is a fully programmable pulse-swallow
type. Following a sensitive (50 mV, −13 dBm) input
amplifier, the RF signal is applied to a 13-bit divider
(MD13 to MD1). The division ratio is provided via the serial
bus to two 13-bit latches, corresponding to transmit and
receive frequencies. The serial programming register is
written to under processor control, independently of divider
operation. This removes difficulty if using a low data bus
transmission speed. The new ratio is transferred to the
appropriate latch when the programming enable signal
(EN) returns HIGH.
The last register bit (PB0) is used to determine whether the
new value is loaded into the transmit (PB0 = 1) or receive
(PB0 = 0) frequency latch. To avoid spurious phase
changes, the divider incorporates the new ratio only at the
end of the on-going reference period. The minimum
division ratio is 512. One reference cycle is required to
update a new ratio. Internal power-on occurs rapidly.
1995 Jul 12
4