TDA4560 Datasheet, PDF (4/9 Pages) NXP Semiconductors – Colour transient improvement circuit

Philips Semiconductors
Colour transient improvement circuit
Product specification
TDA4560
FUNCTIONAL DESCRIPTION
The IC consists of two colour difference channels (B-Y) and (R-Y) and a luminance signal path (Y) as shown in Fig.1.
Colour difference channels
The (B-Y) and (R-Y) colour difference channels consist of a buffer amplifier at the input, a switching stage and an output
amplifier. The switching stages, which are controlled by transient detecting stages (differentiators), switch to a value that
has been stored at the beginning of the transients. The differentiating stages get their signal direct from the colour
difference detecting signal (pins 1 and 2). Two parallel storage stages are incorporated in which the colour difference
signals are stored during the transient time of the signal. After a time of about 600 ns they are switched immediately
(transient time of 150 ns) to the outputs. The colour difference channels are not attenuated.
Y-signal path
The Y-signal input (pin 17) is capacitively coupled to an input clamping circuit. Gyrator delay cells provide a maximum
delay of 1035 ns including an additional delay of 45 ns via the fine adjustment switch (S1) at pin 13. Three delay cells
are switched with two interstage switches dependent on the voltage at pin 15. Thus three switchable delay times of
90 ns, 180 ns or 270 ns less than the maximum delay time are available. A tuning compensation circuit ensures accuracy
of delay time despite process tolerances. The Y-signal path has a 7 dB attenuation as a normal Y-delay coil and can
replace this completely. The output is fed to pin 12 via a buffer amplifier. An additional output stage provides a signal of
90 ns less delay at pin 11 for the option of velocity modulation.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC)
Supply voltage (pin 10)
Voltage ranges to pin 18 (ground)
at pins 1,2,12,15
at pin 11
at pin 17
Voltage ranges
at pin 7 to pin 6
at pin 8 to pin 9
Currents
at pins 6,9
at I₇, I₈, I₁₁, I₁₂
Total power dissipation
Storage temperature range
Operating ambient temperature range
Note
1. Pins 3, 4, 5, 6, 9, 13 and 14 d.c. potential not published.
V_P = V_10−18 max. 13,2 V
V_n-18
V_11-18
V_17-18
0 to V_P
V
0 to (V_P−3V) V
0 to 7
V
V_7-6
V_8−9
0 to 5 V
0 to 5 V
±I_6,9
P_tot
T_stg
T_amb
max. 15
mA
internally limited
max. 1,1 W
-25 to +150 °C
0 to +70
°C
March 1985
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