PHP125N06LT Datasheet, PDF (4/9 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP125N06LT, PHB125N06LT
1000
ID / A
RDS(ON) = VDS/ID
100
DC
10
BUKX508-55
tp = 10 us
100 us
1 ms
10 ms
100 ms
1
1
10
VDS / V ¹⁰⁰
Fig.3. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Zth / (K/W)
1E+00
0.5
1E-01
0.2
0.1
0.05
1E-02 ^0.02
P_D
tp
D
=
tp
T
0
T
t
1E-03
1E-07
1E-05
1E-03
t/s
1E-01
1E+01
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
Drain current, ID (A)
100 _{10 3.4}
4.0
80
VGS = 3.2 V
3.0
60
2.8
40
2.6
20
2.4
2.2
0
0
2
4
6
8
10
Drain-source voltage, VDS (V)
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
RDS(ON) / mOhm
15
VGS / V =
3
10
5
BUK9508-55
3.2
3.4
3.6
4
5
10
0
0
Fig.6.
20
40
60
80
100
120
ID / A
Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
100
ID/A
80
60
40
Tj/C = 175 25
20
0
0
1
2
3
4
VGS/V
Fig.7. Typical transfer characteristics.
I_D = f(V_GS) ; conditions: V_DS = 25 V; parameter T_j
Transconductance, gfs (S)
120
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100
Drain current, ID (A)
Fig.8. Typical transconductance, T_j = 25 ˚C.
g_fs = f(I_D); conditions: V_DS = 25 V
March 1998
4
Rev 1.400