BUK9610-30 Datasheet, PDF (4/8 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9610-30
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_mb)
ID%
120
110
100
Normalised Current Derating
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_mb); conditions: V_GS ≥ 5 V
ID / A
1000
100
RDS(ON) ^{= VDS / ID}
DC
10
7510-30
tp = 100 us
1 ms
10 ms
100 ms
1
1
10
100
VDS / V
Fig.3. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
1E+01 ^{Zth / (K/W)}
BUKX514-55
1E+00
0.5
0.2
1E-01 ^0.1
0.05
0.02
1E-02
0
P_D
tp
D
=
tp
T
T
t
1E-03
1E-07
1E-05
1E-03
t/s
1E-01
1E+01
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
ID / A
100
64
5
80
60
BUK9510-30
3.5
VGS / V =
3.2
3
40
2.8
2.6
20
2.4
2.2
0
0
2
4
6
8
10
VDS / V
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
RDS(ON) / mOhm
20
15
10
5
9510-30
3.2
3.5
4
5
6
VGS / V =
0
0
20
40
60
80
100
ID / A
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
December 1997
4
Rev 1.100