SAA7373 Datasheet, PDF (37/60 Pages) NXP Semiconductors – Digital servo processor and Compact Disc decoder CD7

Philips Semiconductors
Digital servo processor and Compact Disc
decoder (CD7)
Product specification
SAA7373
REGISTER
4
(motor gain)
ADDRESS
0100
5
(motor bandwidth)
0101
6
(motor output
configuration)
0110
7
(DAC output and
status control)
0111
8 (PLL loop filter
bandwidth)
9
(PLL equalization)
1001
DATA
x000
x001
x010
x011
x100
x101
x110
x111
0xxx
1xxx
xx00
xx01
xx10
xx11
00xx
01xx
10xx
xx00
xx01
xx10
xx11
00xx
01xx
10xx
11xx
xx00
xx10
x0xx
x1xx
0xxx
1xxx
FUNCTION
motor gain G = 3.2
motor gain G = 4.0
motor gain G = 6.4
motor gain G = 8.0
motor gain G = 12.8
motor gain G = 16.0
motor gain G = 25.6
motor gain G = 32.0
disable comparator clock divider
enable comparator clock divider; only if SELLPLL set HIGH
motor f4 = 0.5 × n Hz
motor f4 = 0.7 × n Hz
motor f4 = 1.4 × n Hz
motor f4 = 2.8 × n Hz
motor f3 = 0.85 × n Hz
motor f3 = 1.71 × n Hz
motor f3 = 3.42 × n Hz
motor power maximum 37%
motor power maximum 50%
motor power maximum 75%
motor power maximum 100%
MOTO1, MOTO2 pins 3-state
motor PWM mode
motor PDM mode
motor CDV mode
interrupt signal from servo at STATUS pin
status bit from decoder status register at STATUS pin
DAC data normal value
DAC data inverted value
left channel first at DAC (WCLK normal)
right channel first at DAC (WCLK inverted)
see Table 13
INITIAL⁽¹⁾
reset
−
−
−
−
−
−
−
reset
−
reset
−
−
−
reset
−
−
reset
−
−
−
reset
−
−
−
reset
−
reset
−
reset
−
0011
0001
0010
0100
0101
PLL loop filter equalization
PLL 30 ns over-equalization
PLL 15 ns over-equalization
PLL 15 ns under-equalization
PLL 30 ns under-equalization
reset
−
−
−
−
1998 Jul 06
37