P8XC592 Datasheet, PDF (37/108 Pages) NXP Semiconductors – 8-bit microcontroller with on-chip CAN

Philips Semiconductors
8-bit microcontroller with on-chip CAN
Product specification
P8xC592
13.5.5 STATUS REGISTER (SR)
The contents of the Status Register reflects the status of the CAN-controller. The Status Register appears to the CPU
as a read only memory.
Table 36 Status Register (address 2)
7
6
5
BS
ES
TS
4
3
2
1
0
RS
TCS
TBS
DO
RBS
Table 37 Description of the SR bits
BIT SYMBOL
FUNCTION
7 BS
Bus Status (note 1). If the value of BS is:
HIGH (Bus-OFF), then the CAN-controller is not involved in bus activities.
LOW (Bus-ON), then the CAN-controller is involved in bus activities.
6 ES
Error Status. If the value of ES is:
HIGH (error), then at least one of the Error Counters (see Section 13.6.10) has reached the
CPU Warning limit.
LOW (ok), then both Error Counters have not reached the warning limit.
5 TS
Transmit Status (note 2). If the value of TS is:
HIGH (transmit), then the CAN-controller is transmitting a message.
LOW (idle), then no message is transmitted.
4 RS
Receive Status (note 2). If the value of RS is:
HIGH (receive), then the CAN-controller is receiving a message.
LOW (idle), then no message is received.
3 TCS
Transmission Complete Status (note 3). If the value of TCS is:
HIGH (complete), then last requested transmission has been successfully completed.
LOW (incomplete), then previously requested transmission is not yet completed.
2 TBS
Transmit Buffer Access (note 3). If the value of TBS is:
HIGH (released), then the CPU may write a message into the TBF.
LOW (locked), then the CPU cannot access the Transmit Buffer. A message is either waiting for
transmission or is in the process of being transmitted.
1 DO
Data Overrun (note 4). If the value of DO is:
HIGH (overrun), then both Receive Buffers are full and the first byte of another message should be
stored.
LOW (absent), then no data overrun has occurred since the Clear Overrun command was given.
0 RBS
Receive Buffer Status (note 5). If the value of RBS is
HIGH (full), then this bit is set when a new message is available.
LOW (empty), then no message has become available since the last Release Receive Buffer
command bit was set.
1996 Jun 27
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