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XA-G49 Datasheet, PDF (35/42 Pages) NXP Semiconductors – XA 16-bit microcontroller family 64K FLASH/2K RAM, watchdog, 2 UARTs | |||
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Philips Semiconductors
XA 16-bit microcontroller family
64K Flash/2K RAM, watchdog, 2 UARTs
Preliminary specification
XA-G49
5. This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR strobe. This is not usually the case,
and in most applications this parameter is not used.
6. Please note that the XA-G49 requires that extended data bus hold time (WM0 = 1) to be used with external bus write cycles.
7. Applies only to an external clock source, not when a crystal or ceramic resonator is connected to the XTAL1 and XTAL2 pins.
ALE
PSEN
MULTIPLEXED
ADDRESS AND DATA
UNMULTIPLEXED
ADDRESS
tLHLL
tAVLL tLLPL
tPLPH
tLLAX
tPLIV
tPXIX
tPXIZ
A4âA11 or A4âA19
INSTR IN *
tAVIVA
tIXUA
A0 or A1âA3, A12â19
* INSTR IN is either D0âD7 or D0âD15, depending on the bus width (8 or 16 bits).
Figure 20. External Program Memory Read Cycle (ALE Cycle)
SU01073
ALE
PSEN
MULTIPLEXED
ADDRESS AND DATA
UNMULTIPLEXED
ADDRESS
A4âA11 or A4âA19
INSTR IN *
A0 or A1âA3, A12â19
tAVIVB
A0 or A1âA3, A12â19
* INSTR IN is either D0âD7 or D0âD15, depending on the bus width (8 or 16 bits).
Figure 21. External Program Memory Read Cycle (Non-ALE Cycle)
SU00707
2000 Apr 03
35
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