SAA7140A Datasheet, PDF (35/68 Pages) NXP Semiconductors – High Performance Scaler HPS

Philips Semiconductors
High Performance Scaler (HPS)
Objective specification
SAA7140A; SAA7140B
7.8 VRAM port modes
7.8.1 DATA BURST TRANSFER MODE (FIFO MODE)
Data transfer on the VRAM port is asynchronous
(TTR = 0). This mode can be used for all output formats.
Four signals for communication with the external memory
are provided:
1. HFL flag: the half-full flag of the FIFO output register is
raised when the FIFO contains at least 8 data words
(HFL = HIGH). By setting HFL to logic 1, the
SAA7140A and SAA7140B requests a data burst
transfer, via the external memory controller, that has to
start a transfer cycle within the next 32LLC cycles for
32-bit long word modes (16LLC cycles for
16 and 24-bit modes). If there are pixels in the FIFO at
the end of the line, which are not transferred, the circuit
fills up the FIFO register with ‘fill pixels’ until it is
half-full and sets the HFL flag to request a data burst
transfer. After the transfer is completed, HFL is used in
combination with INCADR to indicate the line
increments.
2. The INCADR output signal is used in combination with
HFL to control horizontal and vertical address
generation for a memory controller. The pulse
sequence depends on field formats
(interlace/non-interlace or odd/even fields) and control
bits OF1 and OF0 (subaddress 01). This means that:
a) HFL = 1 at the rising edge of INCADR: the END OF
LINE is reached; request for line address
increment
b) HFL = 0 at the rising edge of INCADR: the END OF
FIELD/FRAME is reached; request for line and
pixel address reset
3. VCLK input signal to clock the FIFO register output
data VRO(n). New data is placed on the VRO(n) port
with the rising edge of VCLK (see Fig.17).
4. The VOEN input enables output data VRO(n).
The outputs are in 3-state mode at VOEN = HIGH.
VOEN changes only when VCLK is LOW. If VCLK
pulses are applied when VOEN is HIGH, the outputs
remain inactive but the FIFO register accepts the
pulses.
7.8.2
CONTINUOUS DATA TRANSFER MODE (TRANSPARENT
MODE)
Data transfer on the VRAM port can be achieved
synchronously (TTR = 1), controlled by output reference
signals at separate pins (except the α-signal) and a
continuous clock output signal (clock rate of LLC) on the
VCLK pin.
The SAA7140A and SAA7140B delivers a continuously
processed data stream. Consequently, the extended
formats of the VRAM port output are selected (bit FS2 = 1;
see Tables 6 and 7).
The output reference signals have to be used to buffer
qualified preprocessed RGB or YUV video data. The YUV
data is only valid in qualified time slots. Control output
signals (see Tables 6 and 7) are:
• α = keying signal of the chroma keyer (not on extra pin
but in lower byte of VRO output)
• FLDV = odd/even field bit in accordance with the
internal field processing
• VSYV = vertical sync signal, active polarity is defined by
VSYP bit
• HGTV = horizontal gate signal, logic 1 marks the
horizontal direction from XO to (XO + XS) lines
• PXQV = pixel qualifier signal, active polarity is defined
by QPP bit.
Interlaced processing (OF bits, subaddress 01): to support
correctly interlaced data storage, the scaler delivers two
INCADR/HFL sequences in each qualified line and an
additional INCADR/HFL sequence after the vertical reset
sequence at the beginning of an odd field. Consequently,
the scaled lines are automatically stored in the right
sequence.
INCADR timing: the distance from the last half-full request
(HFL) to the INCADR pulse may be longer than 64LLC.
The state of HFL is defined for minimum 2LLC cycles
afterwards.
Monochrome format (see Tables 6 and 7); If TTR = 1 and
FS2 = 1 then Ya = Yb.
7.8.3 I²C-BUS CONTROLLED PSEUDO SLEEP MODE
To reduce the power consumption of the SAA7140A and
SAA7140B during phases, where no scaling operations
are requested in the application, it is possible to switch the
SAA7140A and SAA7140B into a pseudo sleep mode.
This mode can be activated, if the clock input LLCIN is not
used or if the hardware is able to pull the LLCIN input or
the LLCIO pin (in input mode) down to logic 0.
In applications, which do not use LLCIN, then LLCIN
should be connected to ground.
LLC has to be provided continuously.
1996 Sep 04
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