SAA7146A Datasheet, PDF (34/144 Pages) NXP Semiconductors – Multimedia bridge, high performance Scaler and PCI circuit SPCI

Philips Semiconductors
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
Product specification
SAA7146A
Table 11 Main control register 2
OFFSET
(HEX)
NAME
BIT TYPE
DESCRIPTION
Mask word
100 M15 to M00
31 to 16 RW 16-bit mask word for bit-selective writes to the control word; when
read this bits always returns logic 0
Control word
100 RPS_SIG4
15
RPS_SIG3
14
RPS_SIG2
13
RPS_SIG1
12
RPS_SIG0
11
UPLD_D1_B
10
UPLD_D1_A
9
UPLD_BRS
8
−
7
UPLD_HPS_H
6
UPLD_HPS_V
5
UPLD_DMA3
4
UPLD_DMA2
3
UPLD_DMA1
2
UPLD_DEBI
1
UPLD_IIC
0
RW RPS Signal 4
RW RPS Signal 3
RW RPS Signal 2
RW RPS Signal 1
RW RPS Signal 0
RW Upload ‘Video DATA stream handling at port D1_B (54H)’; see
Table 68. To upload ‘Initial setting of Dual D1 Interface (50H)’, this
bit and bit 9 must be set; see Table 66.
RW Upload ‘Video DATA stream handling at port D1_A (54H)’; see
Table 67. To upload ‘Initial setting of Dual D1 Interface (50H)’, this
bit and bit 10 must be set; see Table 66.
RW Upload ‘BRS Control Register (58H)’; see Table 69.
− Reserved; when read this bit always returns a logic 0.
RW Upload ‘HPS Horizontal prescale (68H)’; see Table 79.
Upload ‘HPS Horizontal fine-scale (6CH)’; see Table 81.
Upload ‘BCS control (70H)’; see Table 82.
RW Upload ‘HPS control (5CH)’; see Table 71.
Upload ‘HPS Vertical scale (60H)’; see Table 72.
Upload ‘HPS Vertical scale and gain (64H)’; see Table 73.
Upload ‘Chroma Key range (74H)’; see Table 86.
Upload ‘HPS Outputs and Formats (78H)’; see Table 87.
Upload ‘Clip control (78H)’; see Table 89.
RW Upload ‘Video DMA3 registers’; 30H, 34H, 38H, 3CH, 40H, 44H
and 48H (20 to 16).
RW Upload ‘Video DMA2 registers’; 18H, 1CH, 20H, 24H, 28H, 2CH
and 48H (12 to 8).
RW Upload ‘Video DMA1 registers’; 00H, 04H, 08H, 0CH, 10H, 14H
and 48H (4 to 0).
RW Upload ‘DEBI registers’; 88H, 7CH, 80H, 84H and 48H (28 to 26).
RW Upload ‘I²C-bus registers’; (8CH and 90H).
1998 Apr 09
34