ISP1583 Datasheet, PDF(34/87 Page) NXP Semiconductors – Hi-Speed Universal Serial Bus peripheral controller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ISP1583 Datasheet, PDF (34/87 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus peripheral controller

◁

Philips Semiconductors

ISP1583

Hi-Speed USB peripheral controller

9397 750 13461

Product data

Table 28: OTG register: bit description[1]â¦continued

Bit Symbol

Description

DISCV

Set to logic 1 to discharge VBUS. The device discharges VBUS before

starting a new SRP. The discharge can take as long as 30 ms for

VBUS to be charged less than 0.8 V. This bit must be cleared (write

logic 0) before starting a session end detection.

Set to logic 1 to start VBUS pulsing. This bit must be set for more than

16 ms and must be cleared before 26 ms.

OTG

1 â Enables the OTG function. The VBUS sensing functionality will

be bypassed.

0 â Normal operation. All OTG control bits will be masked. Status

bits are undeï¬ned.

[1] No interrupt is designed for OTG. The VBUS interrupt, however, may assert as a side effect during the

VBUS pulsing (see note 2).

When OTG is in progress, the VBUS interrupt may be set because VBUS is charged over VBUS sensing

threshold or the OTG host has turned on the VBUS supply to the device. Even if the VBUS interrupt is

found during SRP, the device should complete data-line pulsing and VBUS pulsing before starting the

B_session_valid detection.

OTG implementation applies to the device with self-power capability. If the device works in sharing

mode, it should provide a switch circuit to supply power to the ISP1583 core during SRP.

Session Request Protocol (SRP):

The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing

followed by VBUS pulsing. The A-device can detect either data-line pulsing or VBUS

pulsing.

The ISP1583 can initiate the B-device SRP by performing the following steps:

1. Detect initial conditions: read bit INITCOND of the OTG register.

2. Start data-line pulsing: set bit DP of the OTG register to logic 1.

3. Wait for 5 ms to 10 ms.

4. Stop data-line pulsing: set bit DP of the OTG register to logic 0.

5. Start VBUS pulsing: set bit VP of the OTG register to logic 1.

6. Wait for 10 ms to 20 ms.

7. Stop VBUS pulsing: set bit VP of the OTG register to logic 0.

8. Discharge VBUS for about 30 ms: optional by using bit DISCV of the OTG register.

9. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG

disabled.

The B-device must complete both data-line pulsing and VBUS pulsing within 100 ms.

Remark: When disabling, OTG data-line pulsing bit DP and VBUS pulsing bit VP must

be cleared by writing logic 1.

9.2.5 Interrupt Enable register (address: 14h)

This register enables or disables individual interrupt sources. The interrupt for each

endpoint can be individually controlled via the associated bits IEPnRX or IEPnTX,

here n represents the endpoint number. All interrupts can be globally disabled

through bit GLINTENA in the Mode register (see Table 21).

Rev. 03 â 12 July 2004

34 of 87

▷