PCF8811 Datasheet, PDF (33/73 Pages) NXP Semiconductors – 80 x 128 pixels matrix LCD driver

Philips Semiconductors
80 × 128 pixels matrix LCD driver
Product specification
PCF8811
13.3 Reset function
13.3.1 BASIC COMMAND SET
After reset the LCD driver has the following state:
• Display setting E = 0 and DAL = 0
• Address commands X[6:0] = 0 and Y[3:0] = 0
• V_LCD is equal to 0, the HV generator is switched off
(PC[1:0] = 00)
• No offset of the programming range (V_OFF[2:0] = 0)
• HV generator programming (V_PR[5:0] = 0)
• 4 × voltage multiplier (S[1:0] = 00)
• After power-on, RAM data is undefined, the reset signal
does not change the content of the RAM
• All LCD outputs at V_SS (display off)
• Initial display line set to line 0 (L[6:0] = 0)
• Initial row set to ROW 0 (C[6:0] = 0)
• Full display selected (P[6:0] = mux 1 : 80 or 1 : 64)
• Display is not mirrored (MX = 0 and MY = 0)
• Internal oscillator is off
• Power-save mode is on
• No frame calibration is running.
13.3.2 EXTENDED COMMAND SET
After reset the LCD driver has the following state:
• Display settings E = 0 and DAL = 0
• Icons disabled (IC = 0)
• Address counter X[6:0] = 0 and Y[3:0] = 0
• Temperature control mode TC2 (TC[2:0] = 010)
• V_LCD is equal to 0; the HV generator is switched off
(PC[1:0] = 0)
• HV generator programming (V_PR[7:0] = 0)
• 4 × voltage multiplier (S[2:0] = 100)
• Frame-rate frequency (FR[1:0] = 11)
• After power-on, RAM data is undefined, the reset signal
does not change the content of the RAM
• All LCD outputs at V_SS (display off)
• Full display selected (P[6:0] = mux 1 : 80 or 1 : 64)
• Initial display line set to line 0 (L[6:0] = 0)
• Initial row set to ROW 0 (C[6:0] = 0)
• Display is not mirrored (MX = 0; MY = 0)
• Internal oscillator is off
• Power-save mode is on
• Horizontal addressing enabled (V = 0)
• No data order swap (DOR = 0)
• No bottom row swap (BRS = 0)
• Internal oscillator enabled (EC = 0)
• No frame calibration running (OC = 0).
13.4 Power-save mode
In the power-save mode the LCD driver has the following
state:
• All LCD outputs at V_SS (display off)
• Bias generator and V_LCD generator switched off;
external V_LCD can be disconnected
• Oscillator off (external clock possible)
• RAM contents not cleared; RAM data can be written
• V_LCD discharged to V_SS in Power-down mode.
There are two ways to put the chip into power-save mode:
• The display must be off (DON = 0) and all the pixels on
(DAL = 1)
• The power-save mode command is activated.
13.5 Display control
The bits DON, E and DAL select the display mode;
see Table 8.
13.5.1 MX
When MX = 0 the display RAM is written from left to right
(X = 0 is on the left side and X = X max is on the right side
of the display).
When MX = 1 the display RAM is written from right to left
(X = 0 is on the right side and X = X max is on the left side
of the display).
The MX bit has an impact on the way the RAM is written
to. So if a horizontal mirroring of the display is desired, the
RAM must first be rewritten, after changing the MX bit.
13.5.2 MY
When MY = 1, the display is mirrored vertically.
A change of this bit has an immediate effect on the display.
2004 May 17
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