TDA8754 Datasheet, PDF (3/8 Pages) NXP Semiconductors – Triple high speed ADC for LCD drive

Philips Semiconductors
Triple high speed ADC for LCD drive
Objective specification
TDA8754
QUICK REFERENCE DATA
SYMBOL
V_CCA
V_DD
V_CCD
V_CC(O)
V_CCA(PLL)
V_CC(O)(PLL)
I_CCA
I_DD
I_CCD
I_CC(O)
I_CCA(PLL)
I_CC(O)(PLL)
INL
DNL
∆G_amp
t_set
f_clk(max)
f_ref
f_PLL
j_PLL(rms)
D/D_PLL
P_tot
PARAMETER
CONDITIONS
MIN.
analog supply voltage for
4.75
R, G, B channels
logic supply voltage for I²C-bus and
3.0
3-wire interface
digital supply voltage
4.75
output stages supply voltage for
3.0
R, G, B channels
analog PLL supply voltage
4.75
output PLL supply voltage
4.75
analog supply current for
−
R, G, B channels
logic supply current for I²C-bus and
−
3-wire interface
digital supply current
−
output stages supply current for
−
R, G, B channels
analog PLL supply current
−
output PLL supply current
−
DC integral non-linearity
−
DC differential non-linearity
−
gain stability versus temperature
V_ref = 2.5 V with
−
100 ppm/K variation
setting time of the block ADC + AGC input signal setting time −
<1 ns; setting to 1%;
f_i = 85 MHz
maximum conversion rate
170
PLL reference clock frequency
15
output clock frequency
12
maximum PLL phase jitter
−
(RMS value)
PLL divider ratio
512
total power consumption
f_clk = 170 MHz; ramp input −
TYP.
5.0
5.0
5.0
3.3
5.0
5.0
tbf
tbf
tbf
tbf
tbf
tbf
±1
±0.5
−
2.5
−
−
−
0.2
−
tbf
MAX. UNIT
5.25 V
5.25 V
5.25 V
3.6
V
5.25 V
5.25 V
−
mA
−
mA
−
mA
−
mA
−
mA
−
mA
±1.5 LSB
±0.8 LSB
200 ppm/K
3.5
ns
−
MHz
120 kHz
170 MHz
−
ns
4 095
1.2
W
1998 Sep 30
3