TDA8578 Datasheet, PDF (3/13 Pages) NXP Semiconductors – Dual common-mode rejection differential line receiver

Philips Semiconductors
Dual common-mode rejection differential
line receiver
Product specification
TDA8578
BLOCK DIAGRAM
1
INL
INL
5
VCC
16
12
VCC
OUTL
TDA8578
8 _SVRR
6
INR
INR
7
11 _OUTR
9
GND
MBD209
FUNCTIONAL DESCRIPTION
The TDA8578 contains two identical differential amplifiers
with a voltage gain of 0 dB. The device is intended to
receive line input signals. The device has a very high-level
of common-mode rejection and it eliminates ground noise.
The common-mode rejection keeps constant up to high
frequencies. The gain of the amplifiers is fixed at 0 dB. The
inputs have a high-input impedance and the output stage
is a class AB stage with a low-output impedance. For a
large common-mode rejection also at low frequencies, an
electrolytic input capacitor at the negative input pin is
advised. The input impedance is relative high, this would
result in a large settling time of the DC input voltage.
Therefore a quick charge circuit is included that charges
the input capacitor within 0.2 s.
All input and output pins are protected against high
electrostatic discharge conditions (4000 V, 150 pF, 150 Ω).
Fig.1 Block diagram.
PINNING
SYMBOL
INL+
n.c.
n.c.
n.c.
INL−
INR−
INR+
SVRR
GND
n.c.
OUTR
OUTL
n.c.
n.c.
n.c.
V_CC
PIN
DESCRIPTION
1
positive input left
2
not connected
3
not connected
4
not connected
5
negative input left
6
negative input right
7
positive input right
8
half supply voltage
9
ground
10
not connected
11
output right
12
output left
13
not connected
14
not connected
15
not connected
16
supply voltage
INL 1
n.c. 2
n.c. 3
n.c. 4
INL 5
INR 6
INR 7
SVRR 8
16 ^V _CC
15 n.c.
14 n.c.
TDA8578
13 n.c.
12 OUTL
11 OUTR
10 n.c.
9 GND
MBD210
Fig.2 Pin configuration.
1995 Dec 15
3