PDIUSBH11 Datasheet, PDF (3/26 Pages) NXP Semiconductors – Universal Serial Bus Hub

Philips Semiconductors
Universal Serial Bus Hub
Product specification
PDIUSBH11
Analog Transceivers
These transceivers interface directly to the USB cables through
some termination resistors. They are capable of transmitting and
receiving serial data at both “full speed” (12 Mbit/s) and “low speed”
(1.5 Mbit/s) data rates.
Hub Repeater
The hub repeater is responsible for managing connectivity on a per
packet basis. It implements packet signaling connectivity and
resume connectivity.
Low speed devices can be connected to downstream ports since the
repeater will not propagate upstream packets to downstream ports,
to which low speed devices are connected, unless they are
preceded by a PREAMBLE PID.
End of Frame Timers
This block contains the specified EOF1 and EOF2 timers which are
used to detect loss-of-activity and babble error conditions in the hub
repeater. The timers also maintain the low-speed keep-alive strobe
which is sent at the beginning of a frame.
General and Individual Port Controller
The general and individual port controllers together provide status
and control of individual downstream ports. Via the I²C-interface a
microcontroller can access the downstream ports and request or
change the status of each individual port.
Any change in the status or settings of the individual port will result
in an interrupt request. Via an interrupt register, the servicing
microcontroller can look up the downstream port which generated
ENDPOINT DESCRIPTIONS
the interrupt and request its new status. Any port status change can
then be reported to the host via the hub status change (interrupt)
endpoint.
Bit Clock Recovery
The bit clock recovery circuit recovers the clock from the incoming
USB data stream using (4X) over-sampling principle. It is able to
track jitter and frequency drift specified by the USB spec.
Philips Serial Interface Engine (PSIE)
The Philips SIE implements the full USB protocol layer. It is
completely hardwired for speed and needs no firmware intervention.
The functions of this block include: synchronization pattern
recognition, parallel / serial conversion, bit stuffing / destuffing, CRC
checking / generation, PID verification / generation, address
recognition, handshake evaluation / generation.
Memory Management Unit (MMU) and Integrated RAM
The MMU and the integrated RAM is used to handle the large
difference in data-rate between USB, running in burst of 12 Mbit/s
and the I²C interface to the microcontroller, running at 100 kbit/s.
This allows the microcontroller to read and write USB packets at its
own (low) speed through I²C.
I²C Slave Interface
This block implements the necessary I²C interface protocol. A slave
I²C allows for simple micro-coding. An interrupt is used to alert the
microcontroller whenever the PDIUSBH11 needs attention. As a
slave I²C device, the PDIUSBH11 I²C clock: SCL is an input and is
controlled by the microcontroller.
The following table summarizes the endpoints supported by the PDIUSBH11.
FUNCTION
ENDPOINT
NUMBER
ENDPOINT TYPE
TRANSFER TYPE
DIRECTION
MAXIMUM PACKET SIZE
(bytes)
HUB
0
Default
Control
IN, OUT
8
1
Status change
Interrupt
IN
1
EMBEDDED
0
Default
Control
IN, OUT
8
1
Interrupt
Interrupt
IN
8
PIN DESCRIPTION
The PDIUSBH11 has two modes of operation. The first mode
(Mode 0) enables the pins DNx_EN_N to power a LED indicating
the port is enabled. The second mode (Mode 1) utilizes the LED
enable pins as per port overcurrent condition pins.
The voltage level at power up on the TEST1 and TEST2 pins
determine the PDIUSBH11 mode of operation. When both of the
pins are connected to Ground, Mode 0 is enabled. When pins
TEST1 and TEST2 are connected to Vcc, Mode 1 is enabled. Note
that in Mode 1 the pin DN2_EN_N remains an LED enable pin. Pin
TEST3 should always be connected to Ground at all times.
1997 Aug 01
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