MB2652 Datasheet, PDF (3/15 Pages) NXP Semiconductors – Dual octal transceiver/registers, non-inverting 3-State

Philips Semiconductors Products
Dual octal transceiver/registers,
non-inverting (3-State)
LOGIC DIAGRAM
nOEBA
nOEAB
nCPBA
nSBA
nCPAB
nSAB
1of 8 Channels
nA0
1D
C1
Q
1D
C1
Q
Product specification
MB2652
nB0
nA1
nB1
nA2
nB2
nA3
nB3
nA4
DETAIL A X 7
nB4
nA5
nB5
nA6
nB6
nA7
nB7
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
nOEAB nOEBA nCPAB nCPBA nSAB nSBA
nAx
nBx
L
L
H
H or L H or L
X
X
H
↑
↑
X
X
Input
Input
Isolation
Store A and B data
X
H
H
H
↑
↑
H or L
X
X
↑
**
X
Input
Unspecified
output*
Store A, Hold B
Store A in both registers
L
L
X
H or L
↑
L
↑
↑
X
X
X Unspecified
**
output*
Input
Hold A, Store B
Store B in both registers
L
L
L
L
X
X
X
X
L
H or L
X
H
Output
Input
Real time B data to A bus
Stored B data to A bus
H
H
H
X
X
H
H or L
X
L
X
H
X
Input
Output
Real time A data to B bus
Store A data to B bus
H
L
H or L H or L
H
H
Output
Output
Stored A data to B bus
Stored B data to A bus
H=
L=
X=
↑=
*
**
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
If both Select controls (nSAB and nSBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must
be staggered in order to load both registers.
August 23, 1993
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