GTL2003 Datasheet, PDF (3/19 Pages) NXP Semiconductors – 8-bit bidirectional low voltage translator

NXP Semiconductors
6. Pinning information
6.1 Pinning
GTL2003
8-bit bidirectional low voltage translator
GND 1
SREF 2
S1 3
S2 4
S3 5
S4 6
S5 7
S6 8
S7 9
S8 10
GTL2003PW
20 GREF
19 DREF
18 D1
17 D2
16 D3
15 D4
14 D5
13 D6
12 D7
11 D8
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Fig 2. Pin configuration for TSSOP20
terminal 1
index area
SREF 2
19 DREF
S1 3
18 D1
S2 4
17 D2
S3 5
16 D3
GTL2003BQ
S4 6
15 D4
S5 7
14 D5
S6 8
13 D6
S7 9
12 D7
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Transparent top view
Fig 3. Pin configuration for DHVQFN20
6.2 Pin description
Table 3.
Symbol
GND
SREF
S1 to S8
D1 to D8
DREF
GREF
Pin description
Pin
1^[1]
2
3, 4, 5, 6, 7, 8, 9, 10
18, 17, 16, 15, 14, 13, 12, 11
19
20
Description
ground (0 V)
source of reference transistor
Port S1 to Port S8
Port D1 to Port D8
drain of reference transistor
gate of reference transistor
[1] DHVQFN package die supply ground is connected to both GND pin and exposed center pad. GND pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
printed-circuit board in the thermal pad region.
GTL2003_1
Product data sheet
Rev. 01 — 27 July 2007
© NXP B.V. 2007. All rights reserved.
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