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74LVC652 Datasheet, PDF (3/14 Pages) NXP Semiconductors – Octal transceiver/register with dual enable 3-State
Philips Semiconductors
Octal transceiver/register with dual enable (3-State)
Product specification
74LVC652
PIN CONFIGURATION
CP AB 1
S AB 2
OE AB 3
A0 4
A1 5
A2 6
A3 7
A4 8
A5 9
A 6 10
A 7 11
GND 12
24 V CC
23 CP BA
22 S BA
21 OE BA
20 B 0
19 B 1
18 B 2
17 B 3
16 B 4
15 B 5
14 B 6
13 B 7
PIN DESCRIPTION
PIN NUMBER SYMBOL
1
CPAB
2
SAB
3
OEAB
4, 5, 6, 7, 8,
9, 10, 11
A0 to A7
12
GND
20, 19, 18, 17,
16, 15, 14, 13
B0 to B7
21
OEBA
22
SBA
23
CPBA
24
VCC
FUNCTION
‘A’ to ‘B’ clock input
(LOW-to-HIGH, edge-triggered)
Select ‘A’ to ‘B’ source input
Output enable B to A input
(active LOW)
‘A’ data inputs/outputs
Ground (0V)
‘B’ data inputs/outputs
Output enable A to B input
Select ‘B’ to ‘A’ source input
‘B’ to ‘A’ clock input
(LOW-to-HIGH, edge-triggered)
Positive supply voltage
SV00767
FUNCTION TABLE
INPUTS
OEAB OEBA CPAB CPBA
SAB
SBA
L
H
H or L H or L
X
X
L
H
↑
↑
X
X
X
H
↑
H or L
X
X
H
H
↑
↑
L
X
L
X
H or L
↑
X
X
L
L
↑
↑
X
L
L
L
X
X
X
L
L
L
X
H or L
X
H
H
H
X
X
L
X
H
H
H or L
X
H
X
DATA I/O *
A0 to A7
B0 to B7
input
input
input
input
un *
output
un *
output
input
input
output
input
input
output
H
L
H or L H or L
H
H
output
output
* The data output functions may be enabled or disabled by
various signals at the OEAB and OEBA inputs. Data input
functions are always enabled, i.e., data at the bus inputs will
be stored on every LOW-to-HIGH transition on the clock
inputs.
un = unspecified
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
↑ = LOW–to–HIGH level transition
FUNCTION
isolation
store A and B data
store A, hold B,
store A in both registers
hold A, store B,
store B in both registers
real-time B data to A bus
stored B data to A bus
real-time A data to B bus
stored A data to B bus
stored A data to B bus and
stored B data to A bus
1998 Jul 29
3