74HC40102 Datasheet, PDF (3/11 Pages) NXP Semiconductors – 8-bit synchronous BCD down counter

Philips Semiconductors
8-bit synchronous BCD down counter
Product specification
74HC/HCT40102
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
1
2
3
4, 5, 6, 7, 10, 11, 12, 13
8
9
14
15
16
SYMBOL
CP
MR
TE
P₀ to P₇
GND
PL
TC
PE
V_CC
NAME AND FUNCTION
clock input (LOW-to-HIGH, edge-triggered)
asynchronous master reset input (active LOW)
terminal enable input
jam inputs
ground (0 V)
asynchronous preset enable input (active LOW)
terminal count output (active LOW)
synchronous preset enable input (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3