74F835 Datasheet, PDF (3/6 Pages) NXP Semiconductors – 8-bit shift register with 2:1 mux-in, latched B inputs, and serial out

Philips Semiconductors
8-bit shift register with 2:1 mux-in,
latched “B” inputs, and serial out
Product specification
74F835
LOGIC DIAGRAM
13
LE
D0B
D0A ¹⁷
16
D1B
D1A ¹⁹
18
D2B
D2A ²¹
20
D3B
D3A ²³
22
D4B
D4A ⁴
3
D5B
D5A ⁶
5
D6B
D6A ⁸
7
D7B
D7A ¹⁰
9
DE
Q
DE
Q
DE
Q
DE
Q
DE
Q
DE
Q
DE
Q
DE
Q
14
SA/B
1
PE
15
DS
2
CP
V_CC = PIN 24
GND = PIN 12
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
11
DQ
Q7
CP
SF01358
FUNCTION TABLE
OPERATING
MODE
INPUTS
PE CP LE SA/B DnA DnB DS
B
LATCH
INTERNAL
SERIAL REGISTER
Q0
Q1–6
Parallel load
A data
h
X
X
X
H
H
L
↑
X
L
l
X
X
X
L
L
Latch B data
X
h
X
H
X
X
X
X
L
X
X
l
X
L
X
X
Parallel load B data
(from Latch)
L
↑
L
H
X
X
X
X
X
X
h
l
H
L
H
L
Parallel load B data
(Transparent Mode)
X
h
X
L
↑
H
H
X
l
X
h
l
H
L
H
L
Serial Shift
H
↑
X
X
X
X
X
X
h
l
X
X
H
L
H=
L=
h=
l=
X=
qn =
↑=
High voltage level
Low voltage level
High voltage level one setup time prior to the Low-to-High clock transition
Low voltage level one setup time prior to the Low-to-High clock transition
Don’t care
Lower case letters indicate the state of the referenced flop cell one cycle prior to the Low-to-High clock transition
Low-to-High clock transition
qn–1
qn–1
OUTPUT
Q7
H
L
X
X
H
L
H
L
q6
q6
1990 Jan 08
3