74F169 Datasheet, PDF (3/12 Pages) NXP Semiconductors – 4-bit up/down binary synchronous counter

Philips Semiconductors
4-bit up/down binary synchronous counter
Product specification
74F169
LOGIC SYMBOL
3
4
5
6
9
PE
D₀ D₁ D₂ D₃
1
U/D
2
CP
TC
15
7
CEP
10
CET
Q₀ Q₁ Q₂ Q₃
V_CC = Pin 16
GND = Pin 8
14 13 12 11
SF00786
LOGIC SYMBOL (IEEE/IEC)
CTR DIV 16
9
M1 [LOAD]
M2 [COUNT]
1
M3 [UP]
M4 [DOWN]
10
G5
3, 5 CT=15
15
7
G6
4, 5 CT=0
2
2, 3, 5, 6+/C7
2, 4, 5, 6–
3
1, 7D
[1]
4
[2]
5
[4]
6
[8]
14
13
12
11
SF00787
FUNCTIONAL DESCRIPTION
The 74F169 uses edge-triggered J-K-type flip-flops and have no
constraints on changing the control or data input signals in either
state of the clock. The only requirement is that the various inputs
attain the desired state at least a setup time before the rising edge
of the clock and remain valid for the recommended hold time
thereafter. The parallel load operation takes precedence over the
other operations, as indicated in the Mode Select Table. When PE is
Low, the data on the D₀ - D₃ inputs enter the flip-flops on the next
rising edge of the Clock. In order for counting to occur, both CEP
and CET must be Low and PE must be High; the U/D input
determines the direction of counting. The Terminal Count (TC)
output is normally High and goes Low, provided that CET is Low,
when a counter reaches zero in the Count Down mode or reaches
15 in the Count Up mode. The TC output state is not a function of
the Count Enable Parallel (CEP) input level. Since the TC signal is
derived by decoding the flip-flop states, there exists the possibility of
decoding spikes on TC. For this reason the use of TC as a clock
signal is not recommended (see logic equations below).
1) Count Enable = CEP⋅CET⋅PE
2) Up: TC = Q₀⋅Q₃⋅(U/D)⋅CET
3) Down: TC = Q₀⋅Q₁⋅Q₂⋅Q₃⋅(U/D)⋅CET
MODE SELECT — FUNCTION TABLE
INPUTS
CP
U/D
CEP
CET
PE
D_n
↑
X
X
X
l
l
↑
X
X
X
X
X
OUTPUTS
Q_n
TC
L
(1)
H
(1)
OPERATING MODE
Parallel load (Dn→Qn)
↑
h
l
l
h
X
Count Up
(1)
Count Up (increment)
↑
l
l
l
h
X
Count Down
(1)
Count Down (decrement)
↑
X
h
X
h
X
q_n
(1)
Hold (do nothing)
↑
X
X
X
h
X
q_n
H
H = High voltage level steady state
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level steady state
l = Low voltage level one setup time prior to the Low-to-High clock transition
q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
(1) = The TC is Low when CET is Low and the counter is at Terminal Count.
Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL).
1996 Jan 05
3