74AUP1G240 Datasheet, PDF (3/19 Pages) NXP Semiconductors – Low-power inverting buffer/line driver; 3-state

NXP Semiconductors
74AUP1G240
Low-power inverting buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
74AUP1G240
74AUP1G240
OE 1
6 V_CC
OE 1
A2
GND 3
5 V_CC
4Y
001aac525
A2
5 n.c.
GND 3
4Y
001aac539
Transparent top view
Fig 4. Pin configuration SOT353-1 Fig 5. Pin configuration SOT886
(TSSOP5)
(XSON6)
74AUP1G240
OE 1
A2
6 V_CC
5 n.c.
GND 3
4Y
001aaf549
Transparent top view
Fig 6. Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Symbol
OE
A
GND
Y
n.c.
V_CC
Pin description
Pin
TSSOP5
1
2
3
4
-
5
XSON6
1
2
3
4
5
6
7. Functional description
Description
output enable input
data input A
ground (0 V)
data output Y
not connected
supply voltage
Table 4. Function table^[1]
Input
OE
A
L
L
L
H
H
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = Don’t care;
Z = high-impedance OFF-state.
Output
Y
H
L
Z
74AUP1G240_1
Product data sheet
Rev. 01 — 6 November 2006
© NXP B.V. 2006. All rights reserved.
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