PTN3700 Datasheet, PDF (28/41 Pages) NXP Semiconductors – 1.8 V simple mobile interface link bridge IC

NXP Semiconductors
PTN3700
1.8 V simple mobile interface link bridge IC
11.4 High-speed signaling channel
Table 21. High-speed signaling channel SubLVDS output characteristics, Transmitter mode
V_DD = 1.65 V to 1.95 V, T_amb = −40 °C to +85 °C, unless otherwise specified. See Section 13.1 for testing information.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
V_O(dif)
differential output
voltage
see Figure 26
100
150 200
mV
V_O(cm)
common-mode output see Figure 26
voltage
0.8
0.9 1.0
V
V_{O(cm)ripple(p-p)} peak-to-peak ripple
common-mode output
voltage
see Figure 27
−75
-
+75
mV
R_o(dif)
differential output
between complimentary outputs of
80
resistance
any differential pair: CLK+/CLK−;
D0+/D0−; D1+/D1−; D2+/D2−
180 280
Ω
t_r(dif)
differential rise time from 20 % to 80 % of V_O(dif);
see Figure 28
200
-
500
ps
t_f(dif)
differential fall time
from 80 % to 20 % of V_O(dif);
see Figure 28
200
-
500
ps
f_oper
operating frequency
-
-
325
MHz
I_O
output current
output drive current per channel
-
-
4
mA
∆V_O(dif)/V_O(dif) relative differential
output voltage
between CLK+/CLK− and
Dn+/Dn−, referenced to
[1] _−10
-
+10
%
difference
CLK+/CLK−
∆V_O(cm)
common-mode output between CLK+/CLK− and
voltage difference
Dn+/Dn−
−0.1
-
+0.1
V
∆t_r
rise time difference
t_r(CLK+/CLK−) − t_r(Dn+/Dn−)
−100
-
+100
ps
∆t_f
fall time difference
t_f(CLK+/CLK−) − t_f(Dn+/Dn−)
−100
-
+100
ps
I_LO
output leakage current Shutdown or Standby mode
(high-impedance state)
−3.0
-
+3.0
µA
t_bit(CLKH-Q)
bit time from CLK
HIGH to data output
PSS mode; Mode 00 or Mode 01; ^[2][3] N × UI
N × UI N × UI
ps
see Table 5, Figure 31
− 19 % × UI
+ 19 % × UI
PSS mode: Mode 10; see
Table 5, Figure 31
[2][3] _{N × UI}
N × UI N × UI
ps
− 16 % × UI
+ 16 % × UI
t_sk(CLK-Q)
CLK edge to data
output skew time
FSS mode; see Figure 33
[2] _{−16 % × UI 0}
+16 % × UI ps
[1] ∆[%] = -^V----^O----⁽-^d---ⁱ--^f--⁾--^C_V---^L-_O--^K--₍--_d-^–--_i-_f--^V-₎--_C-^O--_L--⁽-_K-^d--ⁱ--^f--⁾--^D----^A---^T---^A-- × 100 %
[2] Mode 00: UI = PCLK period / 30
Mode 01: UI = PCLK period / 15
Mode 10: UI = PCLK period / 10
[3] N is defined as the bit position, where 0 ≤ N ≤ 29 (Mode 00), 0 ≤ N ≤ 14 (Mode 01) or 0 ≤ N ≤ 9 (Mode 10).
PTN3700_1
Product data sheet
Rev. 01 — 14 August 2007
© NXP B.V. 2007. All rights reserved.
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