P83CE559 Datasheet, PDF (28/72 Pages) NXP Semiconductors – Single-chip 8-bit microcontroller

Philips Semiconductors
Single-chip 8-bit microcontroller
Preliminary specification
P83CE559/P80CE559
6.8 Watchdog Timer T3
In addition to Timer T2 and the standard timers, a watchdog timer
(T3) consisting of an 11–bit prescaler and an 8–bit timer is also
incorporated (see Figure 27). The timer is incremented every
1.5 ms, derived from the system clock frequency of 16 MHz by the
following:
f_TIMER
+
12
f_CLK
2048
When a timer overflow occurs, the microcontroller is reset and a
reset output pulse is generated at pin RSTOUT. Also the PLL control
register is reset.
To prevent a system reset the timer must be reloaded in time by the
application software. If the processor suffers a hardware/software
malfunction, the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the processor
running out of control.
The watchdog timer can only be reloaded if the condition flag
WLE = PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The time interval between the timer’s reloading and the occurrence
of a reset depends on the reloaded value. For example, this may
range from 1.5 ms to 0.375 s when using an oscillator frequency of
16 MHz.
In the Idle state the watchdog timer and reset circuitry remain active.
The watchdog timer is controlled by the watchdog enable pin (EW).
A LOW level enables the watchdog timer and disables the
Power–down Mode. A HIGH level disables the watchdog timer and
enables the Power–down Mode.
6.9 Serial I/O
The P8xCE559 is equipped with two independent serial ports: SIO0
and SI01. SIO0 is the full duplex UART port, identical to the
PCB80C51 serial port. SIO1 is an I²C–bus serial I/O interface with
byte oriented master and slave functions.
6.9.1 SIO0 (UART)
SIO 0 is a full duplex serial I/O port – it can transmit and receive
simultaneously. This serial port is also receive–buffered. It can
commence reception of a second byte before the previously
received byte has been read from the receive register. If, however,
the first byte has still not been read by the time reception of the
second byte is complete, one of the bytes will be lost. The SIO0
receive and transmit registers are both accessed via the S0BUF
special function register. Writing to S0BUF loads the transmit
register, and reading S0BUF accesses to a physically separate
receive register. SIO0 can operate in 4 modes:
Mode 0: Serial data is transmitted and received through RXD. TXD
outputs the shift clock. 8 data bits are transmitted/received
(LSB first). The baud rate is fixed at 1/12 of the oscillator
frequency. A write into S0CON should be avoided during a
transmission to avoid spikes on RXD/TXD.
Mode 1: 10 bits are transmitted via TXD or received through RXD:
a start bit (0), 8 data bits (LSB first), and a stop bit(1). On
receive, the stop bit is put into RB8 (S0CON special
function register). The baud rate is variable.
Mode 2: 11 bits are transmitted through TXD or received through
RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit,
the 9th data bit (TB8 in S0CON) can be assigned the
value of 0 or 1. With nominal software, TB8 can be the
parity bit (P in PSW). During a receive, the 9th data bit is
stored in RB8 (S0CON), and the stop bit is ignored. The
baud rate is programmable to either 1/32 or 1/64 of the
oscillator frequency.
Mode 3: 11 bits are transmitted through TXD or received through
RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). Mode 3 is
the same as Mode 2 except the baud rate which is
variable in Mode 3.
In all four modes, transmission is initiated by any instruction that
writes to the S0BUF function register. Reception is initiated in Mode
0 when RI = 0 and REN = 1. In the other three modes, reception is
initiated by the incoming start bit provided that REN = 1.
Modes 2 and 3 are provided for multiprocessor communications. In
these modes, 9 data bits are received with the 9th bit written to RB8.
The 9th bit is followed by the stop bit. The port can be programmed
so that with receiving the stop bit, the serial port interrupt will be
activated if, and only if RB8 = 1.
This feature is enabled by setting bit SM2 in S0CON. This feature
may be used in multiprocessor systems.
For more information about how to use the UART in combination
with the registers S0CON, PCON, IEN0, S0BUF and Timer register
refer to the 80C51 Data Handbook IC20.
1996 Aug 06
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