SC28L194 Datasheet, PDF (27/52 Pages) NXP Semiconductors – Quad UART for 3.3V and 5V supply voltage

Philips Semiconductors
Quad UART for 3.3V and 5V supply voltage
Preliminary specification
SC28L194
Table 29. IVR - Interrupt Vector Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Bits 7:0}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{8 data bits of the Interrupt Vector (IVR)}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{The IVR contains the byte that will be placed on the data bus during}
an IACKN cycle when the GCCR bits (2:1) are set to binary ‘01’.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{This is the unmodified form of the interrupt vector.}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 30. Modification of the IVR
Bits 7:5
Bits 4:3
Bits 2:0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Always contains}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{bits (7:5) of the IVR}
Will be replaced
with current
interrupt type if IVC
field of GCCR = 3
Replaced with
interrupting channel
number if IVC field of
GCCR > 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{The table above indicates how the IVR may be modified by the}
Table 32. GIBCR - Global Interrupting Byte Count
Register
Bits 7:4
Bits 3:0
Reserved
Channel byte count code
0000 = 1 AND RxRDY status set for RxFIFO
0000 = 1 AND TxRDY status set for TxD
0001 = 2
0010 = 3
.
1111 = 16
A register associated with the interrupting channel as defined in the
CIR. Its numerical value equals the number of bytes minus 1
(count - 1) ready for transfer to the transmitter or transfer from the
receiver. It is undefined for other types of interrupts
interrupting source. The modification of the IVR as it is presented to
the data bus during an IACK cycle is controlled by the setting of the
bits (2:1) in the GCCR (Global Chip Configuration Register)
Table 31. GICR - Global Interrupting Channel
Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Bits 7:3}
Bits 2:0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _Reserved
Channel code
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 000 = a
001 = b
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 010 = c
011 = d
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{A register associated with the interrupting channel as defined in the}
CIR. It contains the interrupting channel code for all interrupts.
Table 33. Global Interrupting Type Register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Bit 7:6}
Bit 5
Receiver Interrupt
Transmitter Interrupt
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{0x - not receiver}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{10 - with receive errors}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{11 - w/o receive errors}
0 - not transmitter
1 - transmitter interrupt
Reserved
read b’00
Bit 4:3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{A register associated with the interrupting channel as defined in the}
Bit 2:0
Other types
000 - not “other” type
001 - Change of State
010 - Address Recognition Event
011 - Xon/Xoff status
100 - Not used
101 - Break Change
11x - do not occur
CIR. It contains the type of interrupt code for all interrupts.
1998 Sep 21
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