SAA7186 Datasheet, PDF (27/44 Pages) NXP Semiconductors – Digital video scaler

Philips Semiconductors
Digital video scaler
Preliminary specification
SAA7186
FS1
to FS0 FIFO output register format select (EFE-bit see “10”):
EFE FS1 FS0
output format (Tables 2 and 3)
0
00
RGB 5-5-5 + alpa; 2×16-bit/pixel; 32-bit word length;
RGB matrix on, VRAM output format
0
01
YUV 4:2:2; 2×16-bit/pixel; 32-bit word length;
RGB matrix off, VRAM output format
0
10
YUV 4:2:2; video test mode; 1×16-bit/pixel; 16-bit word length;
RGB matrix off, optional output format
0
11
monochrome mode; 4×8-bit/pixel; 32-bit word length;
RGB matrix off, VRAM output format
“01 and 04”
XD9
to
“02 and 04”
XS9
to
“03 and 04”
XO8
to
XD0
XS0
XO0
1
00
1
01
1
10
1
11
RGB 5-5-5 + alpa; 1×16-bit/pixel; 16-bit word length;
RGB matrix on, VRAM output + transparent format
YUV 4:2:2 + alpa; 1×16-bit/pixel; 16-bit word length;
RGB matrix off, VRAM output + transparent format
RGB 8-8-8 + alpa; 1×24-bit/pixel; 24-bit word length;
RGB matrix on, VRAM output + transparent format
monochrome mode; 2×8-bit/pixel; 16-bit word length;
RGB matrix off, VRAM output + transparent format
Pixel number per line (straight binary) on output (VRO):
00 0000 0000 to 11 1111 1111 (number of XS pixels as a maximum)
Pixel number per line (straight binary) on inputs (YIN and UVIN):
00 0000 0000 to 11 1111 1111 (number of input pixels per line as maximum)
Horizontal start position (straight binary) of scaling window (take care of active pixel
number per line).
start with 1st pixel after HREF rise = 0 0001 0000 to 1 1111 1111 (010 to 1FF)
window start and window end may be cut by internal delay compensated HREF = 0
phase. XO has to be matched to the internal processing delay to get full scaling range
May 1993
27