P8XC591 Datasheet, PDF (27/160 Pages) NXP Semiconductors – Single-chip 8-bit microcontroller with CAN controller

Philips Semiconductors
Single-chip 8-bit microcontroller with CAN controller
Preliminary Specification
P8xC591
12.3 Communication between PeliCAN controller
and CPU
A 80C51 CPU Interface connects the PeliCAN to the
internal bus of an 80C51 microcontroller. Special Function
Registers, allows a smart and fast access to the PeliCAN
registers and RAM area. Because of the big address range
to be supported, an indirect pointer based addressing is
included allowing a fast register access with address
autoincrement mode. This reduces the needed number of
Special Function Registers to an amount of 5.
• Five Special Function Registers (SFRs)
• Register address generation in auto-increment mode
• Access to the complete address range of the PeliCAN
handbook, full pagewidth
80C51
CORE
read
write
data
address
INTERFACE
CANADR
CANDAT
SFRs
CANCON
CANSTA
CANMOD
CAN CONTROLLER
PeliCAN
MHI020
Fig.11 CPU to CAN Interfacing.
12.3.1 SPECIAL FUNCTION REGISTERS
Via the five Special Function Registers CANADR,
CANDAT, CANMOD, CANSTA and CANCON the CPU
has access to the PeliCAN Block. Note that CANCON and
CANSTA have different registers mapped depending on
the direction of the access.
The PeliCAN registers may be accessed in two different
ways. The most important registers, which should support
software polling or are controlling major CAN functions are
accessible directly as separate SFRs. Other parts of the
PeliCAN Block are accessible using an indirect pointer
mechanism. In order to achieve a high data throughput
even if the indirect access is used, an address
auto-increment feature is included here.
2000 Jul 26
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