SCC68681 Datasheet, PDF (24/29 Pages) NXP Semiconductors – Dual asynchronous receiver/transmitter

Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product data
SCC68681
X1/CLK
CTCLK
RxC
TxC
t_CLK
t_CTC
t_Rx
t_Tx
t_CLK
t_CTC
t_Rx
t_Tx
+5 V
R1
1 kΩ
U1
X1
RESISTOR REQUIRED
WHEN U1 IS A TTL DEVICE
NC
X2
C1 = C2 = 24 pF FOR C_L = 20 pF
X1
3.6864 MHz
X2
SCC68681
3 pF
4 pF
50 TO
150 kΩ
TO INTERNAL CLOCK DRIVERS
NOTE:
C1 AND C2 SHOULD BE BASED ON MANUFACTURER’S SPECIFICATION. PARASITIC CAPACITANCE SHOULD BE
INCLUDED WITH C1 AND C2. R1 IS ONLY REQUIRED IF U1 WILL NOT DRIVE TO X1 INPUT LEVELS
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY:
LOAD CAPACITANCE (C_L):
TYPE OF OPERATION:
2 – 4 MHz
12 – 32 pF
PARALLEL RESONANT, FUNDAMENTAL MODE
Figure 8. Clock timing
SD00725
CSN
(READ OR
WRITE)
V_M
INTERRUPT¹
OUTPUT
t_IR
V_OL +0.5V
V_OL
NOTES:
1. INTRN or OP3 – OP7 when used as interrupt outputs.
2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the mid point of the switching signal, V_M, to
a point 0.5 volts above V_OL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are
pronounced and can greatly affect the resultant measurement.
SD00116
Figure 9. Interrupt timing
2004 Apr 06
24