SC68C94 Datasheet, PDF (24/33 Pages) NXP Semiconductors – Quad universal asynchronous receiver/transmitter QUART

Philips Semiconductors
Quad universal asynchronous receiver/transmitter (QUART)
Product specification
SC68C94
AC ELECTRICAL CHARACTERISTICS⁴
T_A = 25°C; V_CC = 5V ± 10%, unless otherwise specified. Limits shown as nn/nn refer to Commercial/Industrial temperature range. Single
numbers apply to both ranges.
NO. FIGURE
CHARACTERISTIC
LIMITS
Min
Typ
Max
UNIT
1
2
Setup: A[5:0] valid to CEN Low
2
2
Hold: A[5:0] valid after CEN Low⁶
10
ns
45
ns
3
2
Access: Later of CEN Low and RDN Low, to Dnn valid (read)
110/115
ns
4
2
Later of CEN Low and (RDN or WRN as applicable) Low, to DACKN Low
Normal Operation:
10 + 2
X1 edges⁵
From Power Down:
5
2
Earlier of CEN High or RDN High, to Dnn released (read)¹
0
ns
90/122 + 3
X1 edges⁵
150
30
ns
6
2
Earlier of CEN High or (RDN or WRN as applicable) High, to DACKN released
0
30
ns
7
2
Earlier of CEN High or (RDN or WRN as applicable) High, in one cycle, to later
of CEN Low and (RDN or WRN as applicable) Low, for the next cycle
50
ns
8
2
Setup, Dnn valid (write) to later of CEN Low and WRN Low²
–30
ns
9
2
Later of CEN Low and WRN Low, to earlier of CEN High or WRN High
110/115
ns
10
2
Hold: Dnn valid (write) after DACKN Low, CEN High or WRN High³
0
ns
NOTES:
1. The minimum time indicates that read data will remain valid until the bus master drives CEN and/or RDN to High.
2. The fact that this parameter is negative means that the Dnn line may actually become valid after CEN and WRN are both Low.
3. In a Write operation, the bus master must hold the write data valid either until drives CEN and/or WRN to High, or until the QUART drives
DACKN to Low, whichever comes first.
4. Test condition for interrupt and I/O outputs: C_L = 50pF, forced current for V_OL = 5.3mA; forced current for V_OH = 400µA, RL = 2.7kΩ to V_CC.
Test condition for rest of outputs: C_L = 150pF
5. Consecutive write operations to the upper four bits of the Command Register (CR) require at least three X1/CLK edges; four X1/CLK edges
in the ‘X1/CLK divide by 2 edges’ according to register 2E or 2F setting.
6. Address is latched at leading edge of a read or write cycle.
A[5:0]
1
2
READ CYCLE
1
2
WRITE CYCLE
CEN
RDN
WRN
D[7:0]
DACKN
3
3
4
4
7
7
7
7
5
8
5
8
6
6
9
9
9
9
4
4
Figure 2. A Read Cycle Followed by a Write Cycle with DACKN
10
10
10
6
6
SD00181
1995 May 1
24