SC26C198 Datasheet, PDF (23/49 Pages) NXP Semiconductors – Octal UART with TTL compatibility at 3.3V and 5V supply voltages

Philips Semiconductors
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
IMR[7] – Controls if a change of state in the inputs equipped with
input change detectors will cause an interrupt.
IMR[4] – Enables the generation of an interrupt in response to
recognition of an in–band flow control character.
IMR[3] – Reserved
IMR[6] – Controls the generation of an interrupt by the watch-dog
timer event. If set, a count of 64 idle bit times in the receiver will
begin interrupt arbitration.
IMR[2] – Enables the generation of an interrupt when a Break
condition has been detected by the channel receiver.
IMR[1] – Enables the generation of an interrupt when servicing for
IMR[5] – Enables the generation of an interrupt in response to
changes in the Address Recognition circuitry of the Special Mode
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ (multi-drop or wake–up mode).
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Table 13. RxFIFO Receiver FIFO}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _Bit[10]
Bit[9]
Bit[8]
Bits [7:0]
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Break
Received
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _Status
Framing
Error
Status
Parity
Error
Status
8 data bits
MSBs =0 for 7,6,5 bit
data
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ The FIFO for the receiver is 11 bits wide and 16 ”words” deep. The
status of each byte received is stored with that byte and is moved
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{along with the byte as the characters are read from the FIFO. The}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{upper three bits are presented in the STATUS register and they}
the RxFIFO is desired.
IMR[0] – Enables the generation of an interrupt when servicing for
the TxFIFO is desired.
This register provides the 3 MSBs of the Interrupt Arbitration number
for a Change of State, COS, interrupt.
Table 17. BCRx – Bidding Control Register – Xon
Bits 7:3
Bits 2:0
Reserved
MSB of an Xon/Xoff interrupt bid
This register provides the 3 MSBs of the Interrupt Arbitration number
change in the status register each time a data byte is read from the
FIFO. Therefor the status register should be read BEFORE the byte
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{is read from the RxFIFO if one wishes to ascertain the quality of the}
byte
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{The forgoing applies to the ”character error” mode of status}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{reporting. See MR1[5] and ”RxFIFO Status” descriptions for ”block}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ error” status reporting. Briefly ”Block Error” gives the accumulated
error of all bytes received in the RxFIFO since the last “Reset Error”
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{command was issued. (CR = x’04)}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Table 14. TxFIFO – Transmitter FIFO
Bits 7:0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{8 data bits. MSBs set to 0 for 7, 6, 5 bit data}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{The FIFO for the transmitter is 8 bits wide by 16 bytes deep. For}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ character lengths less than 8 bits the upper bits will be ignored by
the transmitter state machine and thus are effectively discarded.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Table 15. BCRBRK – Bidding Control Register –}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Break Change
Bits 7:3
Bits 2:0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _Reserved
MSB of break change interrupt bid
for an Xon/Xoff interrupt.
Table 18. BCRA – Bidding Control Register –
Address
Bits 7:3
Bits 2:0
Reserved
MSB of an address recognition event
interrupt bid
This register provides the 3 MSBs of the Interrupt Arbitration number
for an address recognition event interrupt.
Table 19. XonCR – Xon Character Register
Bits 7:0
8 Bits of the Xon Character Recognition
An 8 bit character register that contains the compare value for an
Xon character.
Table 20. XoffCR – Xoff Character Register
Bits 7:0
8 Bits of the Xoff Character Recognition
An 8 bit character register that contains the compare value for an
This register provides the 3 MSBs of the Interrupt Arbitration number
Xoff character.
for a break change interrupt.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Table 16. BCRCOS – Bidding Control Register –}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Change of State}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Bits 7:3}
Bits 2:0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _Reserved
MSB of a COS interrupt bid
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Read as x’0
Table 21. ARCR – Address Recognition Character
Register
Bits 7:0
8 Bits of the Multi–Drop Address Character Recognition
An 8 bit character register that contains the compare value for the
wake–up address character
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