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LPC2470 Datasheet, PDF (23/72 Pages) NXP Semiconductors – Flashless 16-bit/32-bit micro; Ethernet, CAN, LCD, USB 2.0 device/host/OTG, external memory interface | |||
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NXP Semiconductors
LPC2470
Fast communication chip
Table 4. Pin description â¦continued
Symbol
Pin
Ball
P4[23]/A23/
RXD2/MOSI1
129[1] J15[1]
P4[24]/OE
183[1] B8[1]
P4[25]/WE
179[1] B9[1]
P4[26]/BLS0
119[1]
L15[1]
P4[27]/BLS1
139[1] G15[1]
P4[28]/BLS2/
170[1]
MAT2[0]/LCDVD[6]/
LCDVD[10]/
LCDVD[2]/
TXD3
C11[1]
P4[29]/BLS3/
MAT2[1]
LCDVD[7]/
LCDVD[11]/
LCDVD[3]/RXD3
176[1]
B10[1]
P4[30]/CS0
187[1] B7[1]
P4[31]/CS1
193[1] A4[1]
ALARM
USB_Dâ2
DBGEN
TDO
TDI
TMS
TRST
TCK
RTCK
37[8]
N1[8]
52
U1
9[1]
F4[1]
2[1]
4[1]
6[1]
8[1]
10[1]
D3[1]
C2[1]
E3[1]
D1[1]
E2[1]
206[1] C3[1]
RSTOUT
29
K3
Type
I/O
I/O
I
I/O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
O
O
O
I/O
O
O
O
I
I/O
O
I/O
O
O
I/O
I
O
I
I
I
I
I/O
O
Description
P4[23] â General purpose digital input/output pin.
A23 â External memory address line 23.
RXD2 â Receiver input for UART2.
MOSI1 â Master Out Slave In for SSP1.
P4[24] â General purpose digital input/output pin.
OE â LOW active Output Enable signal.
P4[25] â General purpose digital input/output pin.
WE â LOW active Write Enable signal.
P4[26] â General purpose digital input/output pin.
BLS0 â LOW active Byte Lane select signal 0.
P4[27] â General purpose digital input/output pin.
BLS1 â LOW active Byte Lane select signal 1.
P4 [28] â General purpose digital input/output pin.
BLS2 â LOW active Byte Lane select signal 2.
MAT2[0] â Match output for Timer 2, channel 0.[19]
LCDVD[6]/LCDVD[10]/LCDVD[2] â LCD data.[19]
TXD3 â Transmitter output for UART3.
P4[29] â General purpose digital input/output pin.
BLS3 â LOW active Byte Lane select signal 3.
MAT2[1] â Match output for Timer 2, channel 1.[19]
LCDVD[7]/LCDVD[11]/LCDVD[3] â LCD data.[19]
RXD3 â Receiver input for UART3.
P4[30] â General purpose digital input/output pin.
CS0 â LOW active Chip Select 0 signal.
P4[31] â General purpose digital input/output pin.
CS1 â LOW active Chip Select 1 signal.
ALARM â RTC controlled output. This is a 1.8 V pin. It goes HIGH when
a RTC alarm is generated.
USB_Dâ2 â USB port 2 bidirectional Dâ line.
DBGEN â JTAG interface control signal. Also used for boundary
scanning.
TDO â Test Data out for JTAG interface.
TDI â Test Data in for JTAG interface.
TMS â Test Mode Select for JTAG interface.
TRST â Test Reset for JTAG interface.
TCK â Test Clock for JTAG interface. This clock must be slower than 1â6
of the CPU clock (CCLK) for the JTAG interface to operate.
RTCK â JTAG interface control signal.
Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0])
to operate as Trace port after reset.
RSTOUT â This is a 1.8 V pin. LOW on this pin indicates LPC2470
being in Reset state.
LPC2470_0
Preliminary data sheet
Rev. 00.01 â 5 October 2007
© NXP B.V. 2007. All rights reserved.
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