SC28L92 Datasheet, PDF (22/44 Pages) NXP Semiconductors – 3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter DUART

Philips Semiconductors
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
Product specification
SC28L92
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ CTPL – COUNTER TIMER PRESET REGISTER, LOWER
Bits 7:0
8 LSB of the BRG Timer divisor.
ACR – AUXILIARY CONTROL REGISTER AND CHANGE OF STATE CONTROL
Bit 7
Bit 6:4
Bit 3
Bit 2
Bit 1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{BaudGroup CounterTimermodeandclockselect}
Enable IP3
Enable IP2
Enable IP1
Bit 0
Enable IP0
IPCR – INPUT PORT CHANGE REGISTER
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bit 7
Bit 6
Bit 5
Bit 4
Delta IP3
Delta IP2
Delta IP1
Delta IP0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{IPR – INPUT PORT REGISTER}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Bit 7}
Bit 6
Bit 5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{State of IP}
State of IP 6 State of IP 5
Bit 4
State of IP 4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{SOPR – SET THE OUTPUT PORT BITS (OPR)}
Bit 3
State of IP3
Bit 3
State of IP 3
Bit 2
State of IP2
Bit 2
State of IP 2
Bit 1
State of IP1
Bit 1
State of IP1
Bit 0
State of IP0
Bit 0
State of IP 0
Bit 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Set OP 7
Set OP 6
Set OP 5
Set OP 4
Set OP 3
Set OP 2
Set OP 1
Set OP 0
ROPR – RESET OUTPUT PORT BITS (OPR)
Bit 7
BIT 6
BIT 5
BIT 4
Reset OP 7
Reset OP 6
Reset OP 5
Reset OP 4
BIT 3
Reset OP 3
BIT 2
Reset OP 2
BIT 1
Reset OP 1
BIT 0
Reset OP 0
OPCR OUTPUT PORT CONFIGURATION REGISTER (NOTE OP1 AND OP0 ARE THE RTSN OUTPUT AND
ARE CONTROLLED BY THE MR REGISTER)
Bit 7
BIT 6
BIT 5
BIT 4
BIT(3:2)
BIT(1:0)
Configure OP7
Configure OP6
Configure OP5
Configure OP4
Configure OP3
Configure OP2
REGISTER DESCRIPTIONS Mode Registers
MR0A Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.
Addr
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _MR0A/
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^MR0B
Bit 7
Rx
WATCHDOG
BIT 6
RxINT BIT 2
BITS 5:4
TxINT (1:0)
BIT 3
FIFO SIZE
BIT 2
BAUD RATE
EXTENDED II
BIT 1
TEST 2
BIT 0
BAUD RATE
EXTENDED 1
0x00
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _0x08
0 = Disable
1 = Enable
See Tables in
MR0
description
See Table 4
0 = 8 byte FIFO 0 = Normal
1 = 16 byte FIFO 1 = Extend II
Set to 0
0 = Normal
1 = Extend
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{MR0[7]—This bit controls the receiver watch dog timer. 0 = disable,}
01
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{1 = enable. When enabled, the watch dog timer will generate a}
receiver interrupt if the receiver FIFO has not been accessed within
10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{64 bit times of the receiver 1X clock. This is used to alert the control}
11
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{processor that data is in the RxFIFO that has not been read. This}
3 or more bytes in FIFO
6 or more bytes in FIFO
8 bytes in FIFO (Rx FULL)
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt.
Table 3a. Receiver FIFO interrupt fill
MR0[6]—Bit 2 of receiver FIFO interrupt level. This bit along with Bit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 6 of MR1 sets the fill level of the FIFO that generates the receiver
interrupt.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{MR0[6] MR1[6] Note that this control is split between MR0 and}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{MR1. This is for backward compatibility to the SC2692 and}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ SCN2681.
Table 3. Receiver FIFO interrupt fill level
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{(MR0(3) = 0 (8 bytes)}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{MR0[6] MR1[6]}
Interrupt Condition
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₀₀
1 or more bytes in FIFO (Rx RDY)
level(MR0(3)=1 (16 bytes)
MR0[6] MR1[6]
Interrupt Condition
00
1 or more bytes in FIFO (Rx RDY)
01
8 or more bytes in FIFO
10
12 or more bytes in FIFO
11
16 bytes in FIFO (Rx FULL)
2000 Jan 21
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