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| SCC68692 Datasheet, PDF (21/30 Pages) NXP Semiconductors – Dual asynchronous receiver/transmitter DUART | |||
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Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCC68692
X1/CLK
A1âA4
RWN
CSN
tCSC
tAS
tRWS
tAH
tRWH
tCSW
D0âD7
DTACKN
tDS
tDH
tCSD
tDCW
tDAH
tDAT
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
Figure 5. Bus Timing (Write Cycle)
SD00148
X1/CLK
tCSC
INTRN
IACKN
tDD
tDF
D0âD7
DTACKN
tDAL
tCSD
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
tDCR
tDAH
tDAT
Figure 6. Interrupt Cycle Timing
SD00149
1998 Sep 04
21
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