SAA7335 Datasheet, PDF (21/36 Pages) NXP Semiconductors – DSP for CD and DVD-ROM systems

Philips Semiconductors
DSP for CD and DVD-ROM systems
Preliminary specification
SAA7335
Flags output (CFLG) (open-drain output)
A 1-bit flag signal is available at the CFLG pin, this contains 11 bits running off the ADCCLK, each bit period is 7 ADCCLK
periods. This signal shows the status of the error corrector and interpolator and is updated every frame.
handbook, halfpage
pause
START
bit
data bits
MGK252
Fig.16 Flags output format.
Table 6 Definition of flag bits
BIT
NUMBER
0
1 to 3
4
5
9, 6 to 8
10
VALUE
DESCRIPTION
1
000
001
010
011
100
all others reserved
core fail
root count (3 to 0)
0
START bit
C1 first or C1 last; note 1
C2 first, CD mode reserved, DVD mode; note 1
reserved; note 1
C2 last; note 1
corrector not active; note 1
failure flag set because correction impossible; note 2
flag fail; note 3
this indicates the number of errors corrected; note 4
STOP bit
Notes
1. For DVD mode read PI for C1 and PO for C2.
2. This flag refers to the previous correction frame.
3. This flag refers to the previous correction frame (is not valid i.e. always logic 0 in DVD mode).
4. Bit order of root count is 9, then 6 to 8 for root count (3 to 0).
ABSOLUTE TIME SYNC
The sync signal is the absolute time sync signal. In the CD mode it is the FIFO-passed subcode sync and relates the
position of the subcode sync to the audio data (DAC output). In the DVD mode it indicates the start of a new sector
header.
The flag may be used for special purposes such as synchronization of different players.
1997 Aug 11
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